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X-DMA




What is X-DMA?

X-DMA is a project to connect a PC to the C64/128 in such a way that the exchange of data between the PC and the C64/128 is done by means of DMA.
Products: A card for connecting your C64 with a PC. No soldering on the C64/128 itself needed.

Remark: this idea has never been realized because I ran into the same problem as with my IDE project: it isn't 1541 compatible! I keep the project on my site on request: some people use the tecnical info provided by this project for other things. They are welcome :)


The story

PC-Disk 2.0, the predecessor of CBM-HD, one of my first projects, was not very fast. I could live with it but I decided to develop a faster version: PC-XFER. This interface uses a block of RAM that is accessible from the C64 as well as from the external system. But, due to the enormous amount of ICs needed, I never found the time to build one. Either Marko Makela or Frank Kontros launched the idea to use DMA. The result is this project.


The base

DMA stands for Direct Memory Access. This means that data is transferred from memory or I/O to memory or I/O by other means then by the CPU of that particular system. When DMA is performed, another device or CPU takes complete command of the bus. The REU (RAM Expansion Unit) of Commodore uses DMA to transfer data between this cartridge and the C64. In this case a special C= IC does the job. For the PC users amongst you, DMA is used when loading or saving files from/to your floppy drive or hard disk drive. In case of the PC the processor is stopped and disconnected from the busses and the 8237 DMA-controller takes control of the bus.
A kind of DMA also happens in the C64 all the time; if the VIC (videochip) does not have enough time to read all the data during its normal ratio of time, it simply steals this time by shutting down the 6510 for a few cycles.

The idea behind X-DMA is if the C64/128 wants to load/save data, it is the PC which does the job by reading/writing the data from/to the memory of the C64/128 by means of DMA.


Putting the C64 in DMA mode

Before we can DMA, we have to tristate the 6510. This can be done by negating the DMA-pin at the expansion port. This can NOT be done by the PC, it has to be done by the C64 itself: you have to be sure that the 6510 is not performing a write-action and the tristating must be done in the low half of the systemclock.
The most simple way is to take a flip-flop, a 74LS74, and use one of its output to negate the already mentioned DMA-pin. How is this flip-flop addressed? The most simple way would be to use the IO1 line to activate the flip-flop and IO2 to de-activate it again. Disadvantage: you cannot connect another cartridge to the expansion port parallel to X-DMA. So using an extra decoder within IO1 or IO2 is a more friendly solution but you will need more parts.

IMHO there is a better solution but this means hacking the hardware of C64/128. Please read this document about the $D7xx-area .

In the given schematic I used IO1 for selecting the range. Independent of the chosen range, we use a 74LS138 3-to-8-demultiplexer (U2) to decode the range even further. In this way we can use this range for more purposes. Output Y0 of the 138 is connected with the 'RESET'-input of U1a, a 74LS74 D-flip-flop, and output Y1 with the 'PRESET'-input. The Q-output of the 74 is connected with the DMA-input of the expansion port. To ensure that DMA is NOT active after a reset, we connect the RESET with the CLOCK-input and the DATA-input with +5 Volt. The rising edge of RESET sets the flip-flop this way when the C= is powered up.


The timing

Once the C64/128 is in DMA-mode, the PC can start reading/writing data. But whatever PC we use, it must forfill the needs in timing of the C64 when writing data as well as its own needs when reading it. This means we have to synchronise all the actions.

Output Y5 of U7, a 3-to-8 decoder, outputs a (L) the moment the PC addresses the area $0D000/$0DFFF (you're free to choose an other area of course). Y5 is connected to the IO-RDY input of a PC-slot through U16a, an 74LS32 OR-gate, and a 74LS125 buffer. As the second input of the OR-gate is (L) in a normal situation, the processor is forced to halt as soon as Y5 goes (L).
To make sure that all timing requirements for the C64 are forfilled, we have to wait for the end of PHI2. Because the video-chip can mess up things, we have to involve output BA as well. Y5 is NORred (74LS02, U17a) with the output of U6b, a 74LS08 AND-gate. This gate combines (PHI2 * BA). The resulting signal is used to clock a 74 flip-flop (U1b).
Clocking U1b causes its Q-output to become (H). This signal is ANDed with the output of U6b, /MEMW of the PC-slot and /Q of U1a through U12a, a 74LS20 4-input NAND gate. The output of this gate is used to enable U4, a 74LS541 buffer. U4 outputs the data on the data bus of the PC towards the C64/128.
At the end of the positive half of (PHI2 * BA), the PC is allowed to proceed again. We NAND (U11a, 74LS00 NAND-gate) the Q-output of U1b and the output of U17a and use the output to clock another 74LS74 (U10a). The /Q-output of this 74 becomes (L) which enables U9a, a 74LS393 dual binary counter, to start counting. At the same time the output of U16a becomes (H) as well, enabling the PC to proceed. After two cycles output Qb becomes (H). This signal is inverted through a 74LS04 (U8b). The resulting signal resets U1b that on its turn resets U10a. On its turn /Q of U10a clears the counter. Resetting U10a means clearing the second input of the OR-gate U16a allowing Y5 to stop the PC again until the end of the next positive half of (PHI2 * BA).


Using X-DMA

Using X-DMA is a different story. This involves software for both machines. (stopped.....)





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