Build your own 6502
What is it?
The idea of this project was to build the well known 6502 processor using only normal available TTL ICs. Unfortunately this quickly turned out to be quite impossible seen from a practical view of point (the explanation will follow later). It turned out I had to use some other building blocks as well: (E)EPROMS.Dividing the 6502 in blocks
There isn't a real schematic of the interior of the 6502 available (AFAIK), so I had to make my own based on the "internal architecture of the 6501" published in many datasheets and based on how the 6502 behaves when executing commands. First I divided the 6502 into functional blocks:- CPU in/output
- Instruction decoder
- Program Counter
- Registers A, X and Y
- Static Addresses
- Stackpointer
- Flag register
- ALU
Not being able to make my own PCB's, I spread the blocks as good as possible equally over (now) eight Euro cards (10 * 16 cm). To connect those cards I will use the DIN64-AB connector. Why this particular connector? For the simple reason I have these connectors and according backplane laying around.
Using this connector forced me to reconsider my design as it contained too many busses. IMHO I still have too many busses but having the luxury of a 64-pin connector I will keep it like this. The advantage: a speedier 6502 and more flexebility for future designs.
CPU in/output
This part, to be found on card #1, is the actual interface to the outside world. Connector CON1 represents the 40 pins that should replace the 6502 when you really want to test/use the self-built processor.
One of the most important inputs is PHI0. Because it is needed by many other gates in my design as input and, not being sure if my design will stress the mother system, I buffer it first with a 74125 buffer (IC01a). If it appears it is not needed, I always can bridge it with a wire.
As you can see, PHI1 is created by inverting PHI0 (IC07a). PHI2 is created by inverting PHI1 on its turn (IC07b). Why not using PHI0 as source for PHI2? At this moment I use my experience gathered with my project 6502 -> 65816. A real prototype can confirm whether I am wrong or not.
Two 573's, IC02 and IC03, latch and buffer the address lines. I need the latch function as I need the internal address bus temporarily for other things like preparing it for zero page accesses. The latch function is controlled by the Instruction Decoder using line I01
Two 573's, IC04 and IC05, latch and buffer the data lines. IC04 buffers the data towards the 6502 and is latched by PHI0 so the 6502 still has access to the data when the original data has disappeared. Its Output Control (OC) is controlled by the Instruction decoder (I04).
IC05 is clocked by the Instruction decoder (I00). Its OC is controled by I02 through an OR gate, IC06a (see later).
I03 emulates the R/W-line and is buffered by another 125, IC01c.
As you can see, all outgoing buffers can be tri-stated. This is not a normal feature of the 6502. But some Atari computers have a 6502 clone on board that can be tri-stated. I also want to mention the 6510 (C64), 8501 (C16 and Plus/4) and 8502 (C128), which have this feature as well. Jumper J1 give you the choice to enable or disable this function.
These buffers need an active (H) on their OC ports to tri-state them. The Commodore processors mentioned above need a (L) to tri-state them. So a 04 invreter, IC07d, is used to invert the signal. Resistor R1 makes sure that the input of IC07d has the correct level if the feature isn't needed.
OR gate (IC06a) makes sure that, if demanded from the outside, data buffer IC05 is tri-stated as well.
Instruction-decoder
The instruction decoder, also found on card #1, is that part of the 6502 which controls what element should be activated at a given time for a certain instruction. Some instructions need more then one cycle to be performed due to the fact that to complete it, more data has to be read from to the world outside the 6502 or written to it. For example, the command LDA ($56),Y performs four other reads beside the original read of the opcode.The actual decoder:
As said, the originally idea was to build the 6502 only using TTL-ICs of the 74xxx series. Then I started to calculate the Boolean equations for every element in each functional block. The results were not looking nice at all. For example, the input for incrementing the Program Counter alone needed an AND-gate with more then 41 inputs! Most probably the designers of the 6502 did use this method but there is a big difference in creating a 41-input AND-gate directly in silicon or cascading several normal TTL ICs.
And this is just for one part of one instruction. Imagine you have to create this 41-input AND-gate out of normal 4-input AND-gates and/or 13-input NAND-gates. Practical impossible IMHO.
Not wanting to use fast programmable arrays like PAL's, CPLD's or equivalents, I decided to use EPROMs. I did not think of using them in the first place because of the access-time, 150-300 ns., compared it with the 5-10 ns of the IC's mentioned before, and the possible glitches in the output caused by this 'huge' access time. But then I realized that this access time was not a problem at all for a 1 MHz version: an access time of 300 ns. still leaves us with 200 ns. for the rest of the operations. The problem of the glitches in the output can be solved by using a 573 or 574 latch and creating a circuit that generates the needed pulse for that latch. Remark: 373s and 374 can be used as well, they only have a different pin-out.
In 2009 I could lay my hand on some 70 ns. AT29C010's, 128 KB FlashRAMs; 2 MHz. systems are doable now as well :)
Dealing with the access time
The latches have to be triggered the moment we are sure the signals are stable. First we have to deal with the access time itself. My idea: use a delay line IC (IC15) from a scrapped PC.
The trigger itself has to be a pulse for the 573's. The 574's can do with the rising edge of this pulse. This pulse is created by feeding the outputs of two taps of the delay line to an EXOR gate. This gate outputs the difference in time between these outputs as a pulse:
____________________ ________________
PHI0 ____| |____________________|
. .
. .____________________ ___________
TAP1 ____.____| |____________________|
.<-->. = acesstime
____________________ ________
TAP2 ____________| |____________________|
__ __ __
EXOR _________| |_________________| |_________________| |________
What inputs does the decoder need?
We now have to decide what the decoder needs as input. My thoughts:
- Opcode: the 6502 opcode is 8 bits wide.
- We need to tell the decoder that there is an Interrupt, Reset etc. going on. Instead of feeding it with all these signals as well, we feed them instead of the opcode and use one extra bit to tell the decoder what kind of signals it are. Advantage: we have five bits left for future use. (think of the ABORT input of the 65816)
- Branch: branches need extra information whether a branch should be taken or not, one bit.
- Counter: the counter is used to count the steps of every instruction. AFAIK instructions do not need more then 7 CPU clock cycles which means three bits will do.
- Clock signal PHI2 will serve as the LSB of the counter.
What kind of EPROM/FlashRAM do we need?
According the above 14 bits as input will do. This would mean we can use 27128's or equivalents for the job. But using 27256's or better we can think of expanding the design. Having, now in 2012, 29F020 FlashRAMs (old Pentium-II/III motherboard BIOSes) with four extra inputs at my disposal, I started to think about future expansions. Naturally the 65816 comes to my mind but also the emulation of other CPUs like the Z80 and 68xx series. For the moment my goal will be, if possible, a 100% compatible 6502, but one with extra features. There where possible, because I already built parts of some cards, I will implement some of these features.
Opcode / Reset, NMI, IRQ:
IC09, a 573 8 bits latch, latches the opcode coming from the external data bus via the internal data bus at the falling edge of PHI0 at count 00001. IC12, a 573 as well, latches the processed Reset, NMI and IRQ signal (see later). Both 573's output their date towards the decoder FlashRAMs.
The counter circuit
Having extra inputs at my disposal, I immediatly thought about adding an extra timer bit for larger future opcodes like MULyiply. The base part is IC10a (393: 4 bits binary counter with clear). Together with PHI2 we now have a five bits counter where PHI2 is the LSB. These five bits, good for 15 clock cycles, are directly fed to the bus and serve as inputs for the decoder FlashRAMs.
The outputs of the 393 are also fed to a 4-input NOR gate created out an OR gate, IC06d, and a 3-input NOR gate (IC11b). The output of the NOR gate becomes (H) the moment the 393 outputs a (L) at every output. This signal is AND-ed with PHI0 using IC13c. The result is the "falling edge of PHI0 at count 00001" mentioned above.
Its active (H) CLR input is controlled by the Reset signal signal and the Instruction Decoder.
ReaDY signal
The outputs of the 393 are increased at every falling edge of PHI2. But before PHI2 is fed to the 393, it goes through an OR gate, IC06b. This gate ORs PHI2 with the \Q-output of IC17b, a 74 D-flipflop. This D-flipflop represents the state of RDY at the and of PHI2 and does this by saving the state of RDY at the rising edge of PHI1. If RDY is (L), \Q becomes (H) and blocks all pulses from PHI2 towards the 393.
Resetting the decoder
The idea is that at the last cycle of an instruction two things have to be done:
- prepare the cpu to read the opcode of the next instruction
- reset the counter
The last is done by setting I05. I05, after some processing, is used to clear the 393 at the positive part of PHI2. What kind of processing has to be done? The Reset signal must be able to reset the counter as well. So before the signal reaches the 393, it has to be OR-ed (IC06c) with the inverted (IC07e) Reset signal.
If the counter has been reseted by I05, the clear signal must be disabled again before the falling edge of PHI2 otherwise the 393 won't count anymore. We just happen to have such a signal in our system that can do the trick: the pulse for the FlashRAM latches. This is done using AND gate IC13c: the actual clear signal is reduced to the size of the pulse for the FlashRAMs.
During the just created count 00001 nothing can happen any more as the FlashRAMs already have been latched. That's the reason why the last cycle of the previous instruction has to prepare the cpu to read the opcode of the next instruction.
Now I5 has to be cleared again. This is done at the latch of count 00010. But that won't happen immediatly at the moment the FlashRAM pulse becomes (H) and so we run the risk that the 393 is reset again. By AND-ing I5 with PHI0 as well (IC13a) we make sure that it won't happen as PHI0 is (L) at that moment.
And by accident the output of IC13a can serve as the 6502's SYNC signal.
NMI and IRQ
The signals of these two lines are inverted first and fed to the CLK input of a 74 D-flipflop. Why the CLK input and not CLR or PRE? A D-flipflop has to be used to store the signals because theoretically they can disappear during time the decoder is still handling them. At the end of the proces the decoder has to reset the flipflop. Using PRE as input for example, would immediatly set the flipflop again and forcing the decoder to repeat the whole proces again.
As NMI is a negative edge triggered interrupt, inverter IC07f is needed to feed the positive edge triggered CLK input. IRQ is a level triggered interrupt ie. it is checked at the end of PHI0. IRQ can also be disabled. NOR gate (IC11a) can serve all functions in one go. If the IRQ is still active (L) at the end of PHI0 and the disable bit is inactive (read: low) as well, then the rising edge of the output of the NOR gate will trigger the D-flipflop.
After handling NMI/IRQ, the Flipflop is reseted by I06/I07.
Reset
Reset doesn't suffer the above problems. Better, the decoder cannot start until the Reset signal is inactive again. So in this case it can be connected directly to the PRE input.
After handling Reset, the Flipflop is reseted by I07. Yes, this is the same signal as for resetting the IRQ Flipflop. The idea behind it: after a Reset all Flipflops have to be reset anyway and resetting the IRQ Flipflop, and thus resetting the Reset Flipflop has well, won't hurt.
All three
The three \Q-outputs are latched by IC12 at step 00001. They are also NOR-ed by IC11C. Its output is latched by D-flipflop IC17a. The outputs of this flipflop either activate the outputs of IC09 or those of IC12. The Fliflop is clocked by the inverted signal that latches IC09 and IC12. The signal for IC09, RIND, is used to tell the decoder FlashRAMs whether an IRQ, NMI or Reset is going on or not.
But why is D-flipflop IC17a needed? When missing, imagine that an interrupt is generated in the middle of an instruction. This interrupt will set one of the inputs of the NOR gate IC11c, thus negating its output and thus changing the level of the decoder signal RIND. This on its turn will cause the decoder to read the opcode from IC12 instead of IC09 and that in the middle of an instruction. And that is certainly something we don't want to happen!
The Program Counter (PC)
The PC, to be found on card #2, takes care of the address lines during normal operations. The heart of the PC are four cascaded 191's (IC26..29), pre-loadable 4-bits binary up/down counters. The 6502 only uses them in the "up" mode. Having the ABORT signal in mind, I also provided the means to count backwards.
Because the counters don't have any tri-state capabilities, two 541's 8-bit buffers (IC24, IC25) have been added to provide this function.
The two 573's (IC20, IC21) are needed for the JMP instruction, they store the new address during the moments the original addresses are still needed.
I added some connectors between the 191's and 541 that enable me to read the output of the 191's using 7-segments LED displays.
Here you can see the first use of the 16-bits bus: the high byte part (HB) of the PC is loaded from data bits D8..D15. On card #8 you will find the needed cross links to copy data from lower byte part (LB) of the data bus to the HB and vica versa.
The Static addresses
After a reset, the address $FFFC has to be generated in some way. The same has to happen with a NMI or IRQ, or when the Zero Page or Stack is accessed. IC30 and IC31, two FlashRAMs, provide the needed address bits.These FlashRAMs are fed with the same signals as the FlashRAMs of the Instruction decoder. For the few addresses they have to provide, this is overkill for sure. But an earlier 6502-only solution used several 541's and 244's which inputs were wired according the needed addresses. This solution is simpler and also more flexible for future use; think of the 65816, 6800 and 6809 with extra and slightly different addresses.
Although both ICs know what bytes to output when needed, they cannot control their own output, that is something the decoder still has to do (I16 and I17).
The Stackpointer (SP)
The SP can be found on card #3. You will notice that the hardware of the SP has almost the same setup as the PC; only the "JMP" latches at the inputs are missing. Its outputs are connected to the internal address bus.
You probably immediatly noticed that this Stackpointer is a 16-bits register. As I already have in mind emulating other CPUs like the 65816 and Z80, I need a 16-bits Stackpointer anyway.
In case of the 6502 only the LB is needed and therefore the HB has a seperate output enable signal. When ir real 6502 mode, the HB is disabled and the HB Static address register outputs $01.
In case of calling a subroutine or an interrupt, the momentary address has to be stored on the Stack. But before that is possible, this address has to be stored in a temporary register, I will call it the "Interrupt buffer", because the original address will disappear the moment the Stackpointer claims the address bus. The idea is to do that at the moment the 6502 outputs the address for the new instruction. Two 573's, IC48 and IC49 forfill this purpose.
Remark: I later realised that the moment the "old" address has to be stored on the Stack, it is still present in the Program Counter. So only 541 buffers could have done the trick as well. If the so two freed Instruction decoder outputs are needed later, I always can change the design.
The Registers A, X and Y
This part is easy to describe: three 573's and three 541's serve as register A, X and Y. Why not 573's only? It enables me to read the contents of the registers on the fly using 7-segments displays, something impossible when only using 573's.The ALU
The ALU, to be found on card #4, wouldn't have been quite a problem if the 6502 hadn't the decimal mode. But it has and so far I haven't heard of any ALU-IC capable of dealing with this mode. So the first idea was using EPROMs, and later FlashRAMs.The FlashRAMs need to be able to handle at least the next commands:
- ADC
- ADD
- AND
- ASL
- BIT
- CMP / CPX / CPY
- DEC / DEX / DEY
- EOR
- INC / INX / INY
- LSR
- ORA
- ROL
- ROR
- SBC
This totals 14 commands which means 4 selection bits will do. But I also play with the idea to implement the core of the 65C02 and that CPU has more commands. So an extra command bit is needed.
Needed inputs:
- 5 command bits
- 8 bits 1st operand
- 8 bits 2nd operand
- Zero flag
- Carry flag
- Decimal mode flag
The problem: for a complete 8-bits operation I would need at least 24 inputs and I don't know any 5 Volt FlashRAM with so may inputs. So I thought about using a trick: cascading two FlashRAMs, each handling only four bits.
In the first place I wasn't that happy about using EPROMs at all because of their "huge" access time: cascading two EPROMs with an access time of 150 ns. each would mean I couldn't emulate a 6501 faster than 1 Mhz. Why? The reason is that the second EPROM has to wait for an eventual Carry and/or Zero of the first one. Which means a doubled access time of 300 ns.
But just at that time I could lay my hands on my first FlashRAMs and saw that they were much faster, 70 ns., so I decided to use them (IC70, IC71) instead. The total access time is now 140ns., meaning that a 2, maybe even a 3 MHz. system is possible.
Now only needing at least 16 inputs means that a 29F512 will do. But having 29F010s at hand, I decided to use these so I could have an extra command bit.
Each FlashRAM outputs 4 data bits, a Carry bit, an Overflow bit and a Zero bit; that leaves one bit unused. The overflow bit of the first FlashRAM is not used of course.
Both operands are stored in a 573, IC72 and IC73. Because these ICs don't have to share their output with other ICs, only clocking is needed; I48 and I49.
Signal I59 tells both FlashRAMs when they can output the data to the internal data bus.
A 245 buffers the result towards the data bus. Although the FlashRAMs can be tristated as well, the idea is that the resulting flags are also available after that the FlashRAMs were read.
A 16 bits ALU
Wanting to create a 16-bits 6502 also means I need a 16-bits ALU. I will need it at least to check whether a 16-bits number is zero or not. In the beginning I thought that cascading another two FlashRAMs would ruin my "at least 2 MHz" goal. But after some time I suddenly realised that I'm completely free to insert some wait states in my own design if needed. Problem solved :)The HB part of the ALU is a just a copy of the LB part, so nothing exciting there. But because this expanded 6502 can operate as well in 8-bits as 16-bits mode, it wants to have the according flag information. That means we need IC127, a 257 2-to-1 multiplexxer, to choose the right flags for the moment.
Originally the ALU was combined with the Flag register on one and the same card. But there was no room for expansion anymore so I had to split the design in two cards. Needing to forward some flag signals to the Flag register and having no room left on the backplane bus, I decided to add an header for this purpose.
The Flag register
To be found on card #4. The core of the Flag register (FR) is made out of seven 74 D-flipflops (IC64..67). All flipflops can be (re-)set by the Instruction decoder using the Data- and CLK-input.
In some cases the Data-input is only fed by data from the internal data bus, in other cases it can be either the data bus or data coming from the arithmetical bits Zero, Carry or Overflow from the ALU. The choice is archieved by using IC61, a 157 2-to-1 multiplexer.
Every flipflop has its own clock signal. In this way it is possible to change as well as only one single bit as the complete register in case of a memory move (PLP, RTS, RTI).
The 'Overflow' Fliflop is the only one that can be set by an external signal, SO in this case.
When using an opcode like CLC only one bit has to be set or reset. Where does this bit come from? On card #3 you find a 541 buffer which input are controled by one single Instruction decoder signal, I33. This signal decides whether the buffer outputs $00 or $FF.
Unfortunately we have a timing problem now. If we connect the ID directly to the flipflops, we cannot clock a flipflop at the same time we output the $00 or $FF byte; we would have to wait to the next clock half. But that is a waist of time so I looked if it could be done faster. By using two left-over OR gates we create a rising edge about 20 ns. later then the original signal: enough for the buffer to stabilise its out. (And if it isn't enough, we add a resistor an capacitor)
An OR gate before the flipflop does the rest: it makes sure that a possible clocksignal only gets through to its CLK input if the according signal has been set (L) by the Instruction decoder.
Remark: all 6502 one byte instructions take two complete cycles. Very often I wondered why. If an instruction like CLC indeed needs two halves as I mentioned above (plus an idle fourth one), the two compelte cycles have been explained.
In case of a branch the state of a particular bit is needed to decide whether it should be taken or not. A 151 8-to-1 multiplexer enables the decoder to select the flag needed for a particular branch. The result, BRAD, is fed to the FlashRAMs
In a real 6502, bit 5 isn't used. Having a left over flipflop, why not use it? It is needed for the 65816 anyway, or more precise, the Instruction decoder. Again luck is with us, we have a free input at the 151 multiplexer. So now BRAD can tell the ID if there has to be performed an 8-bits or 16-bits operation.
Personally I never liked the way the 65816 switched between the 8- or 16-bits mode. I prefer to use seperate mnemmonics for the 16-bits mode. But if I ever change my mind, the circuit is present.
The Address adder
See: card #5.
The final address for the instruction LDA $1234,X could be calculated using the ALU. But this instruction only needs four cycli, just the same as LDA $1234. So it seems that an on-the-fly calculation is done and the Instruction decoder decides at a certain moment which address to take: the original one or the calculated one. But this needs a 16-bits ALU. "No problem, we already have one!" I hear you say. But using that one with its huge access time, I can forget 2 MHz operations :(
So how can I do the calculation that fast without using the ALU? My only idea was designing a seperate adder. If you have a better idea, please feel free to tell me!
The basic idea is quit simple: four cascaded 83's (4 bits full adders), IC90..93, do the trick. But because they don't have tri-state outputs and latching capabilities, two 573's were added to complete the design.
The internal address bus or the data bus provide the inputs for the 83's. IC85 and 86, two 573s, latch the address.
An AND gate, IC96a, provides the data for ALL inputs of the high byte of the second operand, IC97, during 8-bits operations. The idea is that for a jump the given byte is added as-is but that for a branch bit 7 is taken in account. A branch is negative if bit 7 of the byte is (H). If that is the case, the combination of I74 and bit 7 set the high byte.
IC89 is explained later.
More "Expanding the 6502"
Using the faster and bigger FlashRAMs instead of the EPROMs I had originally in mind meant that I had extra address lines at my disposal. And, as already said, the idea rose to expand the 6502 with extra opcodes and other nice features.More memory
The 65816 is able to handle 16 MB of memory. The needed eight extra address lines are provided by either the Program Bank Register (PBR), Data Bank Register (DBR) or are all (L) during the access of the Stack. Two 573s provide the means for the both Bank Registers, a 541 takes care of the Stack. They can be found on card #x.
16 bits registers
I already mentioned the use of 16-bits registers. And these upper bytes have to be written/read in one or anotherway to/from the original data bus. Two 573's on card #x take care of this. Why 573's latches and not buffers like the 541? Not having worked out everything completely and having two left over free decoder bits I simply thought that if the latch function wasn't needed, it certainly wouldn't hurt.
Having 16-bits registers also has its impact on indexed addressing. IC89 and 97 enable us to use either 8-bits or 16 bits indexed operations.
Even more registers
Another CPU that I have in mind to emulate is the Z80. What you will notice immediatly is the fact that the Z80 has a lot more registers than the 6502 has. I could solve it by adding more and more 573/541 pairs (or just only 573's) but that would cost a lot of board space. So the idea rose to use two 2 KB SRAMs. One FlashRAM is able to handle 32 16-bits registers. See: card #7.
But thinking things over I realised I had a problem: how could I preform a register-to-register transfer within these SRAMs? There is no way a SRAM can output a byte and store it at another address at the same time. This meant I had to use a temporary register and to perform the whole transfer action in two steps. This meant two extra 573s.
Unfortunately this also meant a second FlashRAM/573 combination. But only needing four bits meant four where left over. Feeding them to the SRAMs as well meant I suddenly had 512 registers at my disposal :)
Extra opcodes
Although now having all these nice new features, a 6502 cannot do anything with them for the simple reason that its original instruction decoder has no bits/commands reserved for them. The 65816 can handle the 16-bits registers but not the SRAM ones. And both the 6502 and 65816 don't support the multiply and divide instruction, two instructions that could be very usefull. The only way they can handle all these new features is adding new instructions.
One could replace the illegal opcodes by new ones but if you want to stay as 6502 compatible as possible, it means you only can use the KILL opcodes; the opcodes that freeze the 6502 completely. But then not that many opcodes have been left to use.
Using a two-byte opcode is an other option. With two/three/four extra address lines we have three/seven/fifteen sets of 256 opcodes at our disposal!
If compatibility is a must, then we can use three-byte opcodes. We then only need one KILL opcode. But there is a price to pay: one extra cycle.
Officially the 65816 hasn't any illegal opcodes but there is a, so far, unused one: WDM. WDM stands for "William D. Mensch", the designer of the 6502 and 65816 and was meant to be used in future 65xxx CPUs. My idea is to use this one as base for the multi-bytes instructions.
The realisation is quite simple: two outputs of IC79, one of the FlashRAM latches, are fed to two D-Flipflops (IC80). Their outputs are fed to the Instruction decoder bus again. To make sure that the now altered input of the ID cannot change the output of the latches within the pulse width of CLKL, the data is clocked into the D-Flipflops on the falling edge of CLKL.
All outputs of the Instruction decoder
Card #1 Instruction decoder
I00 IC05 Clock a byte from internal data bus to the external one (H)
I01 IC02 Clock internal address bus into external buffer (H)
I02 IC05 Enable output towards external data bus (L)
I03 R/W line
I04 IC04 Enable access to internal data bus from outside (L)
I05 SYNC / Clearing the 393 counter (H)
I06 IC17b Clear the NMI flipflop (L)
I07 IC14a Clear the Reset flipflop (L)
IC14b Clear the IRQ flipflop (L)
Card #6 16-bits expansion A, X, Y registers / Address lines A16..23
I08 IC1a \
I09 IC1a -- selection of HB input of A, X or Y register
I10 IC107b \
I11 IC107b -- selection of HB output of A, X or Y register
I12 IC103 Clock data bus into Program Bank Register (H)
I13 IC102 Clock data bus into Data Bank Register (H)
I14 IC107a \
I15 IC107a -- selection of output of Program Bank, Data Bank or zero
Card #2 Program Counter / Static Address
I16 IC30 Enable output LB Static address to internal address bus (L)
I17 IC31 Enable output HB Static address to internal address bus (L)
I18 IC24 Enable LB output PC towards internal address bus (L)
IC25 Enable HB output PC towards internal address bus (L)
I19 IC21 Clock data into LB Program Counter buffer (H)
I20 IC21 Clock data into HB Program Counter buffer (H)
I21 IC26..29 Load data into Program Counter (L)
I22 IC26..29 Signal to tell the PC whether to count up or down
I23 IC26..29 Clock pulse for in/decreasing the Program Counter (/)
Card #3 Stackpointer / A, X, Y registers
I24 IC48 Enable output LB Interrupt buffer towards internal data bus (L)
I25 IC48 Clock LB internal address bus to data bus (H)
IC49 Clock HB internal address bus to data bus (H)
I26 IC49 Enable output HB Interrupt buffer towards internal data bus (L)
I27 IC50 Clock a byte from internal data bus into register A (H)
I28 IC52 Clock a byte from internal data bus into register X (H)
I29 IC54 Clock a byte from internal data bus into register Y (H)
I30 IC60a \
I31 IC60a -- selection of output of A, X or Y register
I32 IC46 Clock pulse for in- or decreasing the SP counter (/)
I33 not used
I34 not used
I35 IC41 Signal to tell the SP whether to count up or down
I36 IC41/42 Pulse for loading data into the LB SP counter (L)
I37 IC43/44 Pulse for loading data into the HB SP counter (L)
I38 IC45 Enable output LB SP towards internal address bus (L)
I39 IC46 Enable output HB SP towards internal address bus (L)
Card #4 Flag register
I40 IC64a Clock bit into Carry bit of Flag register
I41 IC67b Clock bit into Zero bit of Flag register
I42 IC65a Clock bit into IRQ disable bit of Flag register
I43 IC65b Clock bit into Decimal bit of Flag register
I44 IC66a Clock bit into Break bit of Flag register
I45 IC63b Clock bit into 8/16-bits bit of Flag register
I46 IC66b Clock bit into Overflow bit of Flag register
I47 IC67a Clock bit into Negative bit of Flag register
I48 IC63A Clock bit into HiddenCarry bit of Flag register
I49 IC61 Selecting data bus or adder as input for Flag register
I50 IC68 \
I51 IC68 > Selecting one of the Flag register bits as input
I52 IC68 / for the Instruction decoder
I53 IC64b Clock bit into Bit 7 Branch
I54 IC73 Enable output ALU towards databus (L)
I55 not used
Card #5 Address adder
2nd operand
I56 IC84 Enable output LB latch towards address adder (L)
IC81 Enable "zero" buffer towards address adder (needed ???) (L)
I57 IC84 Clock HB data bus into latch (H)
I58 IC89 Enable output HB latch towards address adder (L)
IC97 Enable branch buffer towards address adder (H)
I59 IC84 Clock LB data bus into latch (H)
I60 IC94/95 Clock output adder into latch (needed ???) (H)
I61 IC94 Enable LB output latch adder towards address bus (L)
I62 IC95 Enable HB output latch adder towards address bus (L)
I63 IC96/97 Enable "bit 7" branch (H)
1st operand
I64 IC85 Clock LB address bus into LB address adder (H)
I65 IC86 Clock HB address bus into HB address adder (H)
I66 IC90 Set Carry for addres+1 (H)
I67 IC62/80 Enable output 2nd latch towards address adder (L)
IC85/86 Enable output address latch towards adder (H)
I68 IC87 Clock LB data bus into 1st latch (H)
I69 IC88 Clock HB data bus into ist latch (H)
I70 IC63 Clock LB output 1st latch into LB 2nd latch (H)
I71 IC80 Clock HB output 1st latch into HB 2nd latch (H)
Card #8 ALU
I80 \
I81 \
I82 \ Sets the command mode for all ALU FlashRAMs
I83 /
I84 /
I85 /
I86 IC35/122 Enables output of the buffers towards the internal data bus
I87 IC127 Selects 8-bits or 16-bits mode for the generated flags
I88 IC72 Clock LB data into 1st operand
I89 IC73 Clock LB data into 2nd operand
I90 IC123 Clock HB data into 1st operand
I91 IC124 Clock HB data into 2nd operand
I92 IC128 Enables the output of the data buffer from LB to HB
I93 IC128 Clock LB data towards HB data bus (needed ???)
I94 IC23 Enables the output of the data buffer from HB to LB
I95 IC23 Clock HB data towards LB data bus (needed ???)
Card #4 Flag register
I96 \
I97 \ set/reset Break, Carry, etc. flag
I98 /
I99 /
I100 not used
I101 not used
I102 not used
I103 not used
All instructions step by step
I use the timing given by various datasheets. IMHO some of the instructions could have been executed in less cycles but I can imagine that there must have been a valid reason for doing it as it is.
Code Opcode # of cyclus
Step Action Explanation
-- ALL -
00000 Valid for ALL opcodes (00000 only exists during a reset)
I01 = H Latch data from internal address bus
I03 = H R/W = (H)
I04 = H disable data towards internal data bus
I05 = H Clear 393 counter
I13 = L \
I14 = L -- Select bank 0, adress lines A16.. 23 = $00
I18 = L Output Program Counter to internal address bus
I22 = L Program Counter counts up
I25 = H Latch address bus into Interrupt buffer
I87 = L Selects 8-bits mode for the generated flags
All active (H) signals become (L) including I23, I32
All active (L) signals become (H) including I11, I12
All (/) signals become (L)
00001 Valid for ALL opcodes, as above except:
I04 = L Enable data towards internal data bus
I05 = H Clear 393 counter
I21 = H Disable load stored address into Program Counter
I25 = L Disable latch address in Interrupt buffer
I96 = 1 \
I97 = 1 \ Do nothing with Flag register
I98 = 1 /
I99 = 1 /
00010 Valid for ALL opcodes
I05 = L Reset clear for 393 counter
-0xx RESET ?
00000 Just freeze everything, see above
00001 Same as 00000
00010 Output $FFFC on external address bus
I04 = H Disable data towards internal data bus
I05 = L Reset clear for 393 counter
I16 = L Enable output LB Static address to internal address bus
I17 = L Enable output HB Static address to internal address bus
I18 = H Disable output Program Counter to internal address bus
00011 Read LB reset vector
I04 = L Enable data towards internal data bus
I19 = H Latch LB into Program Counter Buffer
00100 Output $FFFD on external address bus
I19 = L Disable read into Program Counter Buffer
00101 Read HB reset vector
I20 = H Latch HB into Program Counter Buffer
00110 Output found address on the external address bus
I07 = L Clear the IRQ and RESET flipflop
I16 = H Disable output LB Static address to internal address bus
I17 = H Disable output HB Static address to internal address bus
I18 = L Enable output Program Counter to internal address bus
I20 = L Disable read into Program Counter Buffer
I21 = L Load stored address into Program Counter
I25 = H Latch LB address in Interrupt buffer
I26 = H Latch HB address in Interrupt buffer
Reset Break flag
I96 = 1 \
I97 = 0 \ Reset Break flag
I98 = 0 /
I99 = 1 /
00111 End reset, start of new instruction
I05 = H Clear 393 counter
I07 = H IRQ and RESET flipflop in rest
I21 = H Disable load stored address into Program Counter
I25 = L Disable latch LB address in Interrupt buffer
I26 = L Disable latch HB address in Interrupt buffer
I96 = 1 \
I97 = 1 \ Do nothing with Flag register
I98 = 1 /
I99 = 1 /
-10x NMI 6
00010 Prepare to write HB Program Counter to Stack
Address has been stored already in the SP buffers
I02 = L Enable data towards external data bus
I03 = L Set R/W line to WRITE
I04 = H Disable data towards internal data bus
I05 = L Reset clear for 393 counter
I17 = L HB Static address outputs $01 to internal address bus
I18 = H Disable output Program Counter to internal address bus
I26 = L Output HB Interrupt buffer towards HB data bus
I35 = H Stackpointer must count down
I38 = L Enable output LB Stackpointer towards internal address bus
I94 = L Enable the output of the data buffer from HB to LB
I95 = H Clock HB data towards LB data bus
00011 Write HB Program Counter to Stack, same as 00010
00100 Prepare to write LB Program Counter to Stack
Address has been stored already in the SP buffers
I24 = L Output LB Interrupt buffer towards LB data bus
I26 = H Disable output HB Interrupt buffer
I32 = H / = decrease the Stackpointer
I94 = H Disable the output of the data buffer from HB to LB
I95 = L Disable clocking the HB data from the SP buffer
00101 Write LB Program Counter to Stack
I32 = L Reset the Stackpointer counter input
00110 Prepare to write Flag register to Stack
I24 = H Disable output LB Interrupt buffer
I32 = H / = decrease the Stackpointer
I54 = L Output Flag register on internal data bus
00111 Write Flag register to Stack
I32 = L Reset the Stackpointer counter input
01000 Disable all write actions
I02 = H Disable data towards external data bus
I03 = H Set R/W line to READ
I32 = H / = decrease the Stackpointer
I54 = H Disable output Flag register buffer towards databus
Output NMI address $FFFA on the external address bus
I16 = L Enable output LB Static address to internal address bus $FA
I17 = L Enable output HB Static address to internal address bus $FF
01001 Read LB NMI vector
I04 = L Enable data towards internal data bus
I19 = H Latch LB into Program Counter Buffer
I32 = L Reset the Stackpointer counter input
01010 Output NMI address $FFFB on the external address bus
I19 = L Disable read into Program Counter Buffer
01011 Read HB NMI vector
I20 = H Latch HB into Program Counter Buffer
I96 = 0 \
I97 = 0 \ Set Interrupt disable flag
I98 = 1 /
I99 = 0 /
01100 Output found address on the external address bus
I06 = L Clear the NMI flipflop
I16 = H Disable output LB Static address to internal address bus
I17 = H Disable output HB Static address to internal address bus
I18 = L Enable output Program Counter to internal address bus
I20 = L Disable read into Program Counter Buffer
I21 = L Load stored address into Program Counter
I25 = H Latch LB address in Interrupt buffer
I26 = H Latch HB address in Interrupt buffer
I96 = 1 \
I97 = 0 \ Reset Break flag
I98 = 0 /
I99 = 1 /
01101 End reset, start of new instruction
I05 = H Clear 393 counter
I06 = H NMI flipflop in rest
I21 = H Disable load stored address into Program Counter
I25 = L Disable latch LB address in Interrupt buffer
I26 = L Disable latch HB address in Interrupt buffer
I96 = 1 \
I97 = 1 \ Do nothing with Flag register
I98 = 1 /
I99 = 1 /
-110 IRQ 6 Same as NMI except address $FFFE/FFFF is outputted
00 BRK 6 Same as IRQ except Break is set
01100 Output found address on the external address bus
I96 = 0 \
I97 = 0 \ Set Break flag
I98 = 0 /
I99 = 1 /
01 ORA ($xx,X) 6
21 AND ($xx,X) 6
41 EOR ($xx,X) 6
61 ADC ($xx,X) 6
E1 SBC ($xx,X) 6
00010 Store X in LB 2nd operand Address adder
I04 = H Disable data towards internal data bus
I05 = L Reset clear for 393 counter
I23 = H / = increases the Program Counter
I30 = 1 \
I31 = 0 -- output LB X register
I56 = L LB data bus is input 2nd operand address adder
I58 = L The branch buffer is input 2nd operand address adder
I59 = H Clock LB X register into 2nd operand latch
I63 = L Branch buffer outputs $00
00011 Read Zeropage address
I04 = L Enable data towards internal data bus
I23 = L Reset the Program Counter input
I30 = 1 \
I31 = 1 -- disable output X
I59 = L Disable clocking LB X into 2nd operand latch
I60 = H Clock output Address adder into latch
Store read data in LB 2nd latch of 1st operand
I66 = L Address adder outputs calculated address
I67 = L Output 2nd latch towards 1st operand adder
I68 = H Clock LB data bus into 1st latch 1st operand
I70 = H Clock LB 1st latch into LB 2nd latch 1st operand
00100 Output LB result adder to address bus, prepare for reading 1st byte
I17 = L Enable output HB Static address to address bus = $00
I18 = H Disable output Program Counter to internal address bus
I23 = H / = increases the Program Counter
I61 = L Output LB Address adder latch towards address bus
I70 = L Disable clocking LB 1st latch into LB 2nd latch 1st operand
00101 Read 1st byte of indexed address
I23 = L Reset the Program Counter input
00110 Prepare for reading 2nd byte of indexed address
I66 = H Address adder outputs calculated address + 1
I68 = L Disable clocking LB data bus into 1st latch 1st operand
I69 = H Clock HB data bus into 1st latch 1st operand
I92 = L Enable the output of the data buffer from LB to HB
I93 = H Clock LB data towards HB data bus
00111 Read 2nd byte of indexed address
01000 Prepare for reading byte to be processed by instruction
I92 = H Disable output of the data buffer from LB to HB
I93 = L Disable clocking LB data towards HB data bus
2nd operand must be $0000
I56 = H The input for the 2nd operand address adder = $00
I58 = H The branch buffer is input 2nd operand address adder
I63 = L Branch buffer outputs $00
Adder must output the address stored in the 1st latch
I17 = H Disable output HB Static address to internal address bus
I62 = L Output HB Address adder latch towards address bus
I66 = L Address adder outputs calculated address
I67 = L Output 2nd latch towards 1st operand adder
I69 = L Disable clocking HB data bus into 1st latch 1st operand
I70 = H Clock LB 1st latch into LB 2nd latch 1st operand
I71 = H Clock HB 1st latch into HB 2nd latch 1st operand
Copy Accu to 1st operand of ALU
I04 = H Disable data towards internal data bus
I30 = 0 \
I31 = 0 -- output LB A register
I88 = H Clock LB data (= A) into 1st operand ALU
01001 Read byte to be processed by instruction
I04 = L Enable data towards internal data bus
I30 = 1 \
I31 = 1 -- disable output A
I49 = L Select ALU as input for Flag register
I80 = \
I81 = \
I82 = \ Sets the command mode for all ALU FlashRAMs
I83 = /
I84 = /
I85 = /
I87 = L Selects 8-bits mode for the generated flags
I88 = L Disable clocking LB data (= A) into 1st operand ALU
I89 = H Clock LB data (= bytefrom outside) into 2nd operand ALU
01010 Copy result to A
I04 = H Disable data towards internal data bus
I18 = L Enable output Program Counter to internal address bus
I27 = H Clock a byte from internal data bus into register A
I86 = L Output ALU buffers towards the internal data bus
Re/set flags
I41 = L Rising edge of delayd CLKL re/sets Zero flag
I47 = L Rising edge of delayd CLKL re/sets Negative flag
Program Counter is in charge again
I18 = L Enable output Program Counter to internal address bus
I25 = H Latch address bus into Interrupt buffer
I61 = H Disable LB output Address adder latch towards address bus
I62 = H Disable HB output Address adder latch towards address bus
01011 End instruction, start of new one
I04 = L Enable data towards internal data bus
I05 = H Clear 393 counter
I25 = L Disable latch address in Interrupt buffer
I27 = L Disable clocking a byte from internal data bus into A
I41 = H No action with Zero flag
I47 = H No action with Negative flag
I86 = H Disable output ALU buffers towards the internal data bus
02 Unknown
03 Unknown
04 Unknown
05 ORA $xx
25 AND $xx
45 EOR $xx
65 ADC $xx
E5 SBC $xx
00010 Prepare reading the Zeropage address
I05 = L Reset clear for 393 counter
I23 = H / = increases the Program Counter
2nd operand must be $0000
I56 = H The input for the 2nd operand address adder = $00
I58 = H The branch buffer is input 2nd operand address adder
I63 = L Branch buffer outputs $00
00011 Read Zeropage address
I23 = L Reset the Program Counter input
I60 = H Clock output Address adder into latch
Store read data in LB 2nd latch of 1st operand
I66 = L Address adder outputs calculated address
I67 = L Output 2nd latch towards 1st operand adder
I68 = H Clock LB data bus into 1st latch 1st operand
I70 = H Clock LB 1st latch into LB 2nd latch 1st operand
00100 Output LB result adder to address bus, prepare for reading byte
I17 = L Enable output HB Static address to address bus = $00
I18 = H Disable output Program Counter to internal address bus
I23 = H / = increases the Program Counter
I61 = L Output LB Address adder latch towards address bus
I70 = L Disable clocking LB 1st latch into LB 2nd latch 1st operand
Copy Accu to 1st operand of ALU
I04 = H Disable data towards internal data bus
I30 = 0 \
I31 = 0 -- output LB A register
I88 = H Clock LB data (= A) into 1st operand ALU
00101 Read byte to be processed by instruction
I04 = L Enable data towards internal data bus
I23 = L Reset the Program Counter input
I30 = 1 \
I31 = 1 -- disable output A
I49 = L Select ALU as input for Flag register
I80 = \
I81 = \
I82 = \ Sets the command mode for all ALU FlashRAMs
I83 = /
I84 = /
I85 = /
I87 = L Selects 8-bits mode for the generated flags
I88 = L Disable clocking LB data (= A) into 1st operand ALU
I89 = H Clock LB data (= bytefrom outside) into 2nd operand ALU
00110 Copy result to A
I04 = H Disable data towards internal data bus
I27 = H Clock a byte from internal data bus into register A
I86 = L Output ALU buffers towards the internal data bus
I89 = L Disable clocking LB data into 2nd operand ALU
Re/set flags
I41 = L Rising edge of delayd CLKL re/sets Zero flag
I47 = L Rising edge of delayd CLKL re/sets Negative flag
Program Counter is in charge again
I18 = L Enable output Program Counter to internal address bus
I25 = H Latch address bus into Interrupt buffer
I61 = H Disable LB output Address adder latch towards address bus
I62 = H Disable HB output Address adder latch towards address bus
00111 End instruction, start of new one
I04 = L Enable data towards internal data bus
I05 = H Clear 393 counter
I25 = L Disable latch address in Interrupt buffer
I27 = L Disable clocking a byte from internal data bus into A
I41 = H No action with Zero flag
I47 = H No action with Negative flag
I86 = H Disable output ALU buffers towards the internal data bus
06 ASL $xx
26 ROL $xx
46 LSR $xx
66 ROR $xx
00010 Prepare reading the Zeropage address
I05 = L Reset clear for 393 counter
I23 = H / = increases the Program Counter
2nd operand must be $0000
I56 = H The input for the 2nd operand address adder = $00
I58 = H The branch buffer is input 2nd operand address adder
I63 = L Branch buffer outputs $00
00011 Read Zeropage address
I23 = L Reset the Program Counter input
I60 = H Clock output Address adder into latch
Store read data in LB 2nd latch of 1st operand
I66 = L Address adder outputs calculated address
I67 = L Output 2nd latch towards 1st operand adder
I68 = H Clock LB data bus into 1st latch 1st operand
I70 = H Clock LB 1st latch into LB 2nd latch 1st operand
00100 Output LB result adder to address bus, prepare for reading byte
I17 = L Enable output HB Static address to address bus = $00
I18 = H Disable output Program Counter to internal address bus
I23 = H / = increases the Program Counter
I61 = L Output LB Address adder latch towards address bus
I70 = L Disable clocking LB 1st latch into LB 2nd latch 1st operand
00101 Read byte to be processed by instruction
I23 = L Reset the Program Counter input
I49 = L Select ALU as input for Flag register
I80 = \
I81 = \
I82 = \ Sets the command mode for all ALU FlashRAMs
I83 = /
I84 = /
I85 = /
I87 = L Selects 8-bits mode for the generated flags
I89 = H Clock LB data (= bytefrom outside) into 2nd operand ALU
00110 Prepare to output the result
I02 = L Enable data towards external data bus
I03 = L Set R/W line to WRITE
I04 = H Disable data towards internal data bus
I86 = L Output ALU buffers towards the internal data bus
I89 = L Disable clocking LB data into 2nd operand ALU
Re/set flags
I41 = L Rising edge of delayd CLKL re/sets Zero flag
I47 = L Rising edge of delayd CLKL re/sets Negative flag
00111 Output the result
01000 Restore address bus
I02 = H Disable data towards external data bus
I03 = H Set R/W line to READ
I86 = H Disable output ALU buffers towards the internal data bus
Program Counter is in charge again
I18 = L Enable output Program Counter to internal address bus
I25 = H Latch address bus into Interrupt buffer
I61 = H Disable LB output Address adder latch towards address bus
01001 End instruction, start of new one
I04 = L Enable data towards internal data bus
I05 = H Clear 393 counter
I25 = L Disable latch address in Interrupt buffer
I27 = L Disable clocking a byte from internal data bus into A
I41 = H No action with Zero flag
I47 = H No action with Negative flag
I86 = H Disable output ALU buffers towards the internal data bus
07 Unknown
08 PHP
00010 Prepare to write Flag register to Stack
I02 = L Enable data towards external data bus
I03 = L Set R/W line to WRITE
I04 = H Disable data towards internal data bus
I05 = L Reset clear for 393 counter
I17 = L HB Static address outputs $01 to internal address bus
I18 = H Disable output Program Counter to internal address bus
I23 = H / = increases the Program Counter
I35 = H Stackpointer must count down
I38 = L Enable output LB Stackpointer towards internal address bus
00011 Write Flag register to Stack, same as 00010
00100 Disable all write actions
I02 = H Disable data towards external data bus
I03 = H Set R/W line to READ
I04 = L Enable data towards internal data bus
I32 = H / = decrease the Stackpointer
I54 = H Disable output Flag register buffer towards databus
00101 End reset, start of new instruction
I05 = H Clear 393 counter
I32 = L Reset the Stackpointer counter input
09 ORA #$xx 2
29 AND #$xx
49 EOR #$xx
69 ADC #$xx
E9 SBC #$xx
00010 Prepare reading the byte
I05 = L Reset clear for 393 counter
I23 = H / = increases the Program Counter
Copy Accu to 1st operand of ALU
I04 = H Disable data towards internal data bus
I30 = 0 \
I31 = 0 -- output LB A register
I88 = H Clock LB data (= A) into 1st operand ALU
00011 Read the byte
I04 = L Enable data towards internal data bus
I23 = L Reset the Program Counter input
I30 = 1 \
I31 = 1 -- disable output A
I49 = L Select ALU as input for Flag register
I80 = \
I81 = \
I82 = \ Sets the command mode for all ALU FlashRAMs
I83 = /
I84 = /
I85 = /
I87 = L Selects 8-bits mode for the generated flags
I88 = L Disable clocking LB data (= A) into 1st operand ALU
I89 = H Clock LB data (= bytefrom outside) into 2nd operand ALU
00100 Copy result to A
I04 = H Disable data towards internal data bus
I25 = H Latch address bus into Interrupt buffer
I27 = H Clock a byte from internal data bus into register A
I86 = L Output ALU buffers towards the internal data bus
I89 = L Disable clocking LB data into 2nd operand ALU
Re/set flags
I41 = L Rising edge of delayd CLKL re/sets Zero flag
I47 = L Rising edge of delayd CLKL re/sets Negative flag
00101 End instruction, start of new one
I04 = L Enable data towards internal data bus
I05 = H Clear 393 counter
I25 = L Disable latch address in Interrupt buffer
I27 = L Disable clocking a byte from internal data bus into A
I41 = H No action with Zero flag
I47 = H No action with Negative flag
I86 = H Disable output ALU buffers towards the internal data bus
0A ASL 2
2A ROL
4A LSR
6A ROR
00010 Copy A into ALU
I05 = L Reset clear for 393 counter
I23 = H / = increases the Program Counter
Copy Accu to 1st operand of ALU
I04 = H Disable data towards internal data bus
I30 = 0 \
I31 = 0 -- output LB A register
I49 = L Select ALU as input for Flag register
I80 = \
I81 = \
I82 = \ Sets the command mode for all ALU FlashRAMs
I83 = /
I84 = /
I85 = /
I87 = L Selects 8-bits mode for the generated flags
I88 = H Clock LB data (= A) into 1st operand ALU
00011 Copy result into A
I23 = L Reset the Program Counter input
I30 = 1 \
I31 = 1 -- disable output A
I27 = H Clock a byte from internal data bus into register A
I86 = L Output ALU buffers towards the internal data bus
Re/set flags
I40 = L Rising edge of delayd CLKL re/sets Carry flag
I41 = L Rising edge of delayd CLKL re/sets Zero flag
I47 = L Rising edge of delayd CLKL re/sets Negative flag
00100 Prepare for next instruction
I25 = H Latch address bus into Interrupt buffer
I27 = L Disable clocking a byte from internal data bus into A
I40 = H No action with Carry flag
I41 = H No action with Zero flag
I47 = H No action with Negative flag
I86 = H Disable output ALU buffers towards the internal data bus
00101 End instruction, start of new one
I04 = L Enable data towards internal data bus
I05 = H Clear 393 counter
I25 = L Disable latch address in Interrupt buffer
0B Unknown
0C Unknown
0D ORA $xxxx
2D AND $xxxx
4D EOR $xxxx
6D ADC $xxxx
ED SBC $xxxx
00010 Prepare reading the LB address
I05 = L Reset clear for 393 counter
I23 = H / = increases the Program Counter
2nd operand must be $0000
I56 = H The input for the 2nd operand address adder = $00
I58 = H The branch buffer is input 2nd operand address adder
I63 = L Branch buffer outputs $00
00011 Read LB address
I23 = L Reset the Program Counter input
I60 = H Clock output Address adder into latch
Store read data in LB 2nd latch of 1st operand
I66 = L Address adder outputs calculated address
I67 = L Output 2nd latch towards 1st operand adder
I68 = H Clock LB data bus into 1st latch 1st operand
I70 = H Clock LB 1st latch into LB 2nd latch 1st operand
00100 Prepare reading the HB address
I23 = H / = increases the Program Counter
I70 = L Disable clocking LB 1st latch into LB 2nd latch 1st operand
00101 Read LB address
I23 = L Reset the Program Counter input
Store read data in LB 2nd latch of 1st operand
I69 = H Clock HB data bus into 1st latch 1st operand
I71 = H Clock HB 1st latch into HB 2nd latch 1st operand
00110 Output result adder to address bus, prepare for reading byte
I18 = H Disable output Program Counter to internal address bus
I23 = H / = increases the Program Counter
I61 = L Output LB Address adder latch towards address bus
I62 = L Output HB Address adder latch towards address bus
I71 = L Disable clocking HB 1st latch into HB 2nd latch 1st operand
Copy Accu to 1st operand of ALU
I04 = H Disable data towards internal data bus
I30 = 0 \
I31 = 0 -- output LB A register
I88 = H Clock LB data (= A) into 1st operand ALU
00111 Read byte to be processed by instruction
I04 = L Enable data towards internal data bus
I23 = L Reset the Program Counter input
I30 = 1 \
I31 = 1 -- disable output A
I49 = L Select ALU as input for Flag register
I80 = \
I81 = \
I82 = \ Sets the command mode for all ALU FlashRAMs
I83 = /
I84 = /
I85 = /
I87 = L Selects 8-bits mode for the generated flags
I88 = L Disable clocking LB data (= A) into 1st operand ALU
I89 = H Clock LB data (= bytefrom outside) into 2nd operand ALU
01000 Copy result to A
I04 = H Disable data towards internal data bus
I27 = H Clock a byte from internal data bus into register A
I86 = L Output ALU buffers towards the internal data bus
I89 = L Disable clocking LB data into 2nd operand ALU
Re/set flags
I41 = L Rising edge of delayd CLKL re/sets Zero flag
I47 = L Rising edge of delayd CLKL re/sets Negative flag
Program Counter is in charge again
I18 = L Enable output Program Counter to internal address bus
I25 = H Latch address bus into Interrupt buffer
I61 = H Disable LB output Address adder latch towards address bus
I62 = H Disable HB output Address adder latch towards address bus
01001 End instruction, start of new one
I04 = L Enable data towards internal data bus
I05 = H Clear 393 counter
I25 = L Disable latch address in Interrupt buffer
I27 = L Disable clocking a byte from internal data bus into A
I41 = H No action with Zero flag
I47 = H No action with Negative flag
I86 = H Disable output ALU buffers towards the internal data bus
0E ASL $xxxx
2E ROL $xxxx
4E LSR $xxxx
6E ROR $xxxx
00010 Prepare reading the LB address
I05 = L Reset clear for 393 counter
I23 = H / = increases the Program Counter
2nd operand must be $0000
I56 = H The input for the 2nd operand address adder = $00
I58 = H The branch buffer is input 2nd operand address adder
I63 = L Branch buffer outputs $00
00011 Read LB address
I23 = L Reset the Program Counter input
I60 = H Clock output Address adder into latch
Store read data in LB 2nd latch of 1st operand
I66 = L Address adder outputs calculated address
I67 = L Output 2nd latch towards 1st operand adder
I68 = H Clock LB data bus into 1st latch 1st operand
I70 = H Clock LB 1st latch into LB 2nd latch 1st operand
00100 Prepare reading the HB address
I23 = H / = increases the Program Counter
I70 = L Disable clocking LB 1st latch into LB 2nd latch 1st operand
00101 Read LB address
I23 = L Reset the Program Counter input
Store read data in LB 2nd latch of 1st operand
I69 = H Clock HB data bus into 1st latch 1st operand
I71 = H Clock HB 1st latch into HB 2nd latch 1st operand
00110 Output result adder to address bus, prepare for reading byte
I18 = H Disable output Program Counter to internal address bus
I23 = H / = increases the Program Counter
I61 = L Output LB Address adder latch towards address bus
I62 = L Output HB Address adder latch towards address bus
I71 = L Disable clocking HB 1st latch into HB 2nd latch 1st operand
Copy Accu to 1st operand of ALU
I04 = H Disable data towards internal data bus
I30 = 0 \
I31 = 0 -- output LB A register
I88 = H Clock LB data (= A) into 1st operand ALU
00111 Read byte to be processed by instruction
I23 = L Reset the Program Counter input
I49 = L Select ALU as input for Flag register
I80 = \
I81 = \
I82 = \ Sets the command mode for all ALU FlashRAMs
I83 = /
I84 = /
I85 = /
I87 = L Selects 8-bits mode for the generated flags
I89 = H Clock LB data (= bytefrom outside) into 2nd operand ALU
01000 Prepare to output the result
I02 = L Enable data towards external data bus
I03 = L Set R/W line to WRITE
I04 = H Disable data towards internal data bus
I86 = L Output ALU buffers towards the internal data bus
I89 = L Disable clocking LB data into 2nd operand ALU
Re/set flags
I41 = L Rising edge of delayd CLKL re/sets Zero flag
I47 = L Rising edge of delayd CLKL re/sets Negative flag
01001 Output the result
01010 Restore address bus
I02 = H Disable data towards external data bus
I03 = H Set R/W line to READ
I86 = H Disable output ALU buffers towards the internal data bus
Program Counter is in charge again
I18 = L Enable output Program Counter to internal address bus
I25 = H Latch address bus into Interrupt buffer
I61 = H Disable LB output Address adder latch towards address bus
I62 = H Disable HB output Address adder latch towards address bus
01011 End instruction, start of new one
I04 = L Enable data towards internal data bus
I05 = H Clear 393 counter
I25 = L Disable latch address in Interrupt buffer
I27 = L Disable clocking a byte from internal data bus into A
I41 = H No action with Zero flag
I47 = H No action with Negative flag
I86 = H Disable output ALU buffers towards the internal data bus
6 1L inc PC
1H ADT-L = DB
2L inc PC
2H ADT-H = DB
3L enable ADT
3H disable ALU ALU-in1 = DB
4L -
4H DB-out DB = ALU_out
5L activate ALU
5H DB = ALU-out
6L inc PC
adjust ST-flags
--- Fast mode ---
5 1L inc PC
1H ADT-L = DB
2L inc PC
2H ADT-H = DB
3L enable ADT
3H ALU-in1 = DB
4L -
4H DB-out DB = ALU-out
5L inc PC
adjust ST-flags
0F Unknown
10 BPL $xx
30 BMI $xx
50 BVC $xx
70 BVS $xx
90 BCC $xx
B0 BCS $xx
D0 BNE $xx
F0 BEQ $xx
2++ 1L inc PC
ACTION = (condition = True)
1H ALU-in1 = DB
2L inc PC ALU-in2 = AD-L
if ACTION
2H latch bit 7 en C AD-L = ALU-out
3L enable AD-load(L)
bit 7 C Action:
0 0 ACTION = 0
0 1 ALU-in1 = $01 ACTION = 1
1 0 ALU-in1 = $FF ACTION = 1
1 1 ACTION = 0
if ACTION
3H ALU-in2 = AD-H
4L enable AD-load(H) AD-H = ALU-out
11 ORA ($xx),Y
31 AND ($xx),Y
51 EOR ($xx),Y
71 ADC ($xx),Y
F1 SBC ($xx),Y
5+ 1L inc PC
1H ADT-L = DB
2L disable ADT-load
disable ADT-C
enable ADT
2H ALU-in2 = DB
3L inc ADT-L ALU-in1 = Y
3H ADT-H-l = DB
4L ena. ADT-load(L) ADT-L = ALU-out
ACTION = Carry
4H ena. ALU-inAC ALU-in1 = DB
5L inc PC AC = ALU-out
adjust ST-flags
if no ACTION enable PC
if ACTION inc ADT-H
5H ALU-in1 = DB
6L adjust ST-flags AC = ALU-out
--- Fast mode ---
5 1L inc PC
1H ADT-L = DB
2L disable ADT-load
disable ADT-C
enable ADT
2H ALU-in2 = DB
3L inc ADT-L ALU-in1 = Y
3H ADT-H-l = DB
4L ena. ADT-load(L) ADT-L = ALU-out
ACTION = Carry
if ACTION inc ADT-H
4H ena. ALU-inAC ALU-in1 = DB
5L inc PC AC = ALU-out
adjust ST-flags
12 Unknown
13 Unknown
14 Unknown
15 ORA $xx,X
35 AND $xx,X
55 EOR $xx,X
75 ADC $xx,X
F5 SBC $xx,X
4 1L inc PC ALU-in2 = X
1H ALU-in1 = DB
ADT-L = DB
2L enable ADT
2H -
3L ADT-L = ALU-out
3H ena. ALU-inAC ALU-in1 = DB
4L inc PC AC = ALU-out
adjust ST-flags
--- Fast mode ---
3 1L inc PC ALU-in2 = X
1H ALU-in1 = DB
2L enable ADT ADT-L = ALU-out
2H ena. ALU-inAC ALU-in1 = DB
3L inc PC AC = ALU-out
adjust ST-flags
16 ASL $xx,X
36 ROL $xx,X
56 LSR $xx,X
76 ROR $xx,X
6 1L inc PC ALU-in2 = X
1H ALU-in1 = DB
ADT-L = DB
2L enable ADT
2H -
3L ADT-L = ALU-out
3H disable ALU ALU-in1 = DB
4L -
4H DB-out DB = ALU-out
5L activate ALU
5H DB = ALU-out
6L inc PC
adjust ST-flags
--- Fast mode ---
6 1L inc PC ALU-in2 = X
1H ALU-in1 = DB
2L enable ADT ADT-L = ALU-out
2H ALU-in1 = DB
3L -
3H DB-out DB = ALU-out
4L inc PC
adjust ST-flags
17 Unknown
18 CLC
38 SEC
58 CLI
78 SEI
B8 CLV
D8 CLD
F8 SED
2 1L inc PC 'action on Flag'
1H -
2L -
--- Fast mode ---
1 1L inc PC 'action on Flag'
19 ORA $xxxx,Y
39 AND $xxxx,Y
59 EOR $xxxx,Y
79 ADC $xxxx,Y
F9 SBC $xxxx,Y
4+ 1L inc PC
1H ALU-in1 = DB
2L inc PC ALU-in2 = Y
2H ADT-H = DB
3L ADT-L = ALU-out
ACTION = Carry
3H ena. ALU-inAC ALU-in1 = DB
4L inc PC AC = ALU-out
if no ACTION enable PC
if ACTION inc ADT-H
4H ALU-in1 = DB
5L adjust ST-flags AC = ALU-out
--- Fast mode ---
4 1L inc PC
1H ALU-in1 = DB
2L inc PC ALU-in2 = Y
2H ADT-H = DB
3L ADT-L = ALU-out
ACTION = Carry
if ACTION inc ADT-H
3H ena. ALU-inAC ALU-in1 = DB
4L inc PC AC = ALU-out
adjust ST-flags
1A Unknown
1B Unknown
1C Unknown
????? samenvoegen met 19 ????
1D ORA $xxxx,X
3D AND $xxxx,X
5D EOR $xxxx,X
7D ADC $xxxx,X
FD SBC $xxxx,X
4 1L inc PC
1H ALU-in1 = DB
2L inc PC ALU-in2 = X
2H ADT-H = DB
3L ADT-L = ALU-out
ACTION = Carry
3H ena. ALU-inAC ALU-in1 = DB
4L inc PC AC = ALU-out
if no ACTION enable PC
if ACTION inc ADT-H
4H ALU-in1 = DB
5L adjust ST-flags AC = ALU-out
1E ASL $xxxx,X
3E ROL $xxxx,X
5E LSR $xxxx,X
7E ROR $xxxx,X
7 1L inc PC
1H ALU-in1 = DB
2L inc PC ALU-in2 = X
2H ADT-H = DB
3L ADT-L = ALU-out
ACTION = Carry
3H disable ALU ALU-in1 = DB
4L -
if ACTION inc ADT-H
ALU-in1 = DB
5H disable ALU ALU-in1 = DB
5L -
5H DB-out DB = ALU-out
6L activate ALU
6H DB = ALU-out
7L inc PC
adjust ST-flags
--- Fast mode ---
5 1L inc PC
1H ALU-in1 = DB
2L inc PC ALU-in2 = X
2H ADT-H = DB
3L ADT-L = ALU-out
ACTION = Carry
if ACTION inc ADT-H
3H ALU-in1 = DB
4L -
4H DB-out DB = ALU-out
5L inc PC
adjust ST-flags
1F Unknown
20 JSR $xxxx 6 1L inc PC
1H AD-L-l = DB
2L enable SP
inc PC
2H - why?
3L -
3H DB-out Stack = AD-H
4L dec SP
4H Stack = AD-L
5L dec SP
enable PC
5H AD-H-l = DB
6L enable AD-load
--- Fast mode ---
5 1L inc PC
1H AD-L-l = DB
2L enable SP
inc PC
2H DB-out Stack = AD-H
3L dec SP
3H Stack = AD-L
4L dec SP
enable PC
4H AD-H-l = DB
5L enable AD-load
21 see $01
22 Unknown
23 Unknown
24 BIT $xx 3 1L inc PC
1H ADT-L = DB
2L enable ADT
ena. ALU-inAC
2H ALU-in1 = DB
3L inc PC
adjust ST-flags
25 see $05
26 see $06
27 Unknown
28 PLP
68 PLA
4 1L inc PC
1H -
2L enable SP
2H Stack -> ST/AC
3L inc SP
3H Stack -> ST/AC
4L enable PC
---Fast mode ---
2 1L inc PC
enable SP
inc SP
1H Stack -> ST/AC
2L -
29 see $09
2A see $0A
2B Unknown
2D BIT $xxxx 4 1L inc PC
1H ADT-L = DB
2L inc PC
2H ADT-H = DB
3L enable ADT
ena. ALU-inAC
3H ALU-in1 = DB
4L inc PC
adjust ST-flags
2D see $0D
2E see $0E
2F Unknown
30 see $10
31 see $11
32 Unknown
33 Unknown
34 Unknown
35 see $15
36 see $16
37 Unknown
38 see $18
39 see $19
3A Unknown
3B Unknown
3C Unknown
3D see $1D
3E see $1E
3F Unknown
40 RTI 6 1L inc PC
1H -
2L enable SP
2H -
3L inc SP
3H Stack -> ST
4L inc SP
enable AD-load
4H Stack -> AD-L
5L inc SP
5H Stack -> AD-H
6L enable PC
--- Fast mode ---
4 1L inc PC
inc SP
enable SP
1H Stack -> ST
2L inc SP
enable AD-load
2H Stack -> AD-L
3L inc SP
3H Stack -> AD-H
4L enable PC
41 see $01
42 Unknown
43 Unknown
44 Unknown
45 see $05
46 see $06
47 Unknown
48 PHA
00010 Prepare to write A register to Stack
I02 = L Enable data towards external data bus
I03 = L Set R/W line to WRITE
I04 = H Disable data towards internal data bus
I05 = L Reset clear for 393 counter
I17 = L HB Static address outputs $01 to internal address bus
I18 = H Disable output Program Counter to internal address bus
I23 = H / = increases the Program Counter
I30 = 0 \
I31 = 0 -- output LB A register
I35 = H Stackpointer must count down
00011 Write A register to Stack, same as 00010
00100 Disable all write actions
I02 = H Disable data towards external data bus
I03 = H Set R/W line to READ
I04 = L Enable data towards internal data bus
I30 = 1 \
I31 = 1 -- disable output A
I32 = H / = decrease the Stackpointer
00101 End reset, start of new instruction
I05 = H Clear 393 counter
I32 = L Reset the Stackpointer counter input
49 see $09
4A see $0A
4B Unknown
4C JMP $xxxx 3 1L inc PC
1H AD-L-l = DB
2L inc PC
2H AD-H-l = DB
3L enable AD-load
4D see $0D
4E see $0E
4F Unknown
50 see $10
51 see $11
52 Unknown
53 Unknown
54 Unknown
55 see $15
56 see $16
57 Unknown
58 see $18
59 see $19
5A Unknown
5B Unknown
5C Unknown
5D see $1D
5E see $1E
5F Unknown
60 RTS 6 1L inc PC
1H -
2L enable SP
2H -
3L inc SP
enable AD-load
3H Stack -> AD-L
4L inc SP
4H Stack -> AD-H
5L enable PC
disable AD-load
5H -
6L inc PC
--- Fast mode ---
3 1L enable SP
inc SP
enable AD-load
1H Stack -> AD-L
2L inc SP
2H Stack -> AD-H
3L inc PC
61 see $01
62 Unknown
63 Unknown
64 Unknown
65 see $05
66 see $06
67 Unknown
68 see $28
69 see $09
6A see $0A
6B Unknown
6C JMP ($xxxx) 5 1L inc PC
1H ADT-L = DB
2L inc PC
2H ADT-H = DB
3L enable AD-load
enable ADT
3H AD-H = DB
4L inc ADT
4H AD-L = DB
5L enable PC
6D see $0D
6E see $0E
6F Unknown
70 see $10
71 see $11
72 Unknown
73 Unknown
74 Unknown
75 see $15
76 see $16
77 Unknown
78 see $18
79 see $19
7A Unknown
7B Unknown
7C Unknown
7D see $1D
7E see $1E
7F Unknown
80 Unknown
81 STA ($xx,X) 6 1L inc PC ALU-in1 = X
1H ALU-in2 = DB
ADT-L = DB
2L enable ADT
2H ADT-L = ALU-out
3L disable ADT-load
3H ADT-L-l = DB
4L inc ADT-L
4H ADT-H = DB
5L enable ADT-load
5H DB-out DB = AC
6L inc PC
--- Fast mode ---
6 1L inc PC ALU-in1 = X
1H ALU-in2 = DB
2L enable ADT ADT-L = ALU-out
2H disable ADT-load ADT-L-l = DB
3L inc ADT-L
3H ADT-H-l = DB
4L enable ADT-load
4H DB-out DB = AC
5L inc PC
82 Unknown
83 Unknown
84 STY $xx
85 STA $xx
86 STX $xx
3 1L inc PC
1H ADT-L = DB
2L enable ADT
2H DB-out DB = Y/AC/X
3L inc PC
87 Unknown
88 DEY
C8 INY
2 1L inc PC ALU = Y
1H Y = ALU
2L -
89 Unknown
8A TXA 2 1L inc PC AC = X
1H -
2L -
--- Fast mode ---
1 1L inc PC AC = X
8B Unknown
8C STY $xxxx
8D STA $xxxx
8E STX $xxxx
4 1L inc PC
1H ADT-L = DB
2L inc PC
2H ADT-H = DB
3L enable ADT
3H DB-out DB = Y/AC/X
4L inc PC
DB-in
enable PC
8F Unknown
90 see $10
91 STA ($xx),Y 6 1L inc PC
1H ADT-L = DB
2L disable ADT-load
disable ADT-C
enable ADT
2H ALU-in2 = DB
3L inc ADT-L ALU-in1 = Y
3H ADT-H-l = DB
4L ena. ADT-load(L) ADT-L = ALU-out
ACTION = Carry
4H -
5L -
if ACTION inc ADT-H
5H DB-out DB = AC
6L inc PC
--- Fast mode ---
5 1L inc PC
1H ADT-L = DB
2L disable ADT-load
disable ADT-C
enable ADT
2H ALU-in2 = DB
3L inc ADT-L ALU-in1 = Y
3H ADT-H-l = DB
4L ena. ADT-load(L) ADT-L = ALU-out
ACTION = Carry
if ACTION inc ADT-H
4H DB-out DB = AC
5L inc PC
92 Unknown
93 Unknown
94 STY $xx,X
95 STA $xx,X
96 STX $xx,X
4 1L inc PC ALU-in2 = X
1H ALU-in1 = DB
ADT-L = DB
2L enable ADT
2H -
3L ADT-L = ALU-out
3H DB-out DB = Y/AC/X
4L inc PC
--- Fast mode ---
3 1L inc PC ALU-in2 = X
1H ALU-in1 = DB
2L enable ADT ADT-L = ALU-out
2H DB-out DB = Y/AC/X
3L inc PC
97 Unknown
98 TYA 2 1L inc PC AC = Y
1H -
2L -
--- Fast mode ---
1 1L inc PC AC = Y
99 STA $xxxx,Y
9D STA $xxxx,X
5 1L inc PC
1H ALU-in1 = DB
2L inc PC ALU-in2 = Y/X
2H ADT-H = DB
3L ADT-L = ALU-out
ACTION = Carry
3H -
4L -
if ACTION inc ADT-H
4H DB-out DB = AC
5L inc PC
--- Fast mode ---
4 1L inc PC
1H ALU-in1 = DB
2L inc PC ALU-in2 = Y/X
2H ADT-H = DB
3L ADT-L = ALU-out
ACTION = Carry
if ACTION inc ADT-H
3H DB-out DB = AC
4L inc PC
9A TXS 2 1L inc PC SP = X
1H -
2L -
9B Unknown
9C Unknown
9D see $99
9E Unknown
9F Unknown
A0 LDY #$xx
A2 LDX #$xx
A9 LDA #$xx
2 1L inc PC
1H Y/X/A = DB
2L inc PC
adjust ST-flags
A1 LDA ($xx,X) 6 1L inc PC ALU-in1 = X
1H ALU-in2 = DB
ADT-L = DB
2L enable ADT
2H ADT-L = ALU-out
3L disable ADT-load
3H ADT-L-l = DB
4L inc ADT-L
4H ADT-H = DB
5L enable ADT-load
5H AC = DB
6L inc PC
adjust ST-flags
--- Fast mode ---
6 1L inc PC ALU-in1 = X
1H ALU-in2 = DB
2L enable ADT ADT-L = ALU-out
2H disable ADT-load ADT-L-l = DB
3L inc ADT-L
3H ADT-H-l = DB
4L enable ADT-load
4H AC = DB
5L inc PC
adjust ST-flags
A2 see $A0
A3 Unknown
A4 LDY $xx
A5 LDA $xx
A6 LDX $xx
3 1L inc PC
1H ADT-L = DB
2L enable ADT
2H Y/AC/X = DB
3L inc PC
adjust ST-flags
A7 Unknown
A8 TAY 2 1L inc PC Y = A
1H -
2L -
--- Fast mode ---
1 1L inc PC Y = A
A9 see $A0
AA TAX 2 1L inc PC X = A
1H -
2L -
--- Fast mode ---
1 1L inc PC X = A
AB Unknown
AC LDY $xxxx
AD LDA $xxxx
AE LDX $xxxx
4 1L inc PC
1H ADT-L = DB
2L inc PC
2H ADT-H = DB
3L enable ADT
3H Y/AC/X = DB
4L inc PC
adjust ST-flags
AF Unknown
B0 see $10
B1 LDA ($xx),Y 6 1L inc PC
1H ADT-L = DB
2L disable ADT-load
disable ADT-C
enable ADT
2H ALU-in2 = DB
3L inc ADT-L ALU-in1 = Y
3H ADT-H-l = DB
4L ena. ADT-load(L) ADT-L = ALU-out
ACTION = Carry
4H AC = DB
5L adjust ST-flags
if ACTION inc ADT-H
5H AC = DB
6L adjust ST-flags
inc PC
--- Fast mode ---
5 1L inc PC
1H ADT-L = DB
2L disable ADT-load
disable ADT-C
enable ADT
2H ALU-in2 = DB
3L inc ADT-L ALU-in1 = Y
3H ADT-H-l = DB
4L ena. ADT-load(L) ADT-L = ALU-out
ACTION = Carry
if ACTION inc ADT-H
5H AC = DB
6L adjust ST-flags
inc PC
B2 Unknown
B3 Unknown
B4 LDY $xx,X
B5 LDA $xx,X
4 1L inc PC ALU-in2 = X
1H ALU-in1 = DB
ADT-L = DB
2L enable ADT
2H -
3L ADT-L = ALU-out
3H Y/A = DB
4L inc PC
--- Fast mode ---
3 1L inc PC ALU-in2 = X
1H ALU-in1 = DB
2L enable ADT ADT-L = ALU-out
2H Y/A = DB
3L inc PC
B6 LDX $xx,Y 4 1L inc PC ALU-in2 = Y
1H ALU-in1 = DB
ADT-L = DB
2L enable ADT
2H -
3L ADT-L = ALU-out
3H X = DB
4L inc PC
--- Fast mode ---
3 1L inc PC ALU-in2 = Y
1H ALU-in1 = DB
2L enable ADT ADT-L = ALU-out
2H X = DB
3L inc PC
B7 Unknown
B8 see $18
B9 LDA $xxxx,Y
BE LDX $xxxx,Y
5 1L inc PC
1H ALU-in1 = DB
2L inc PC ALU-in2 = Y
2H ADT-H = DB
3L ADT-L = ALU-out
ACTION = Carry
3H AC/X = DB
4L adjust ST-flags
if no ACTION enable PC
if ACTION inc ADT-H
4H AC/X = DB
5L adjust ST-flags
inc PC
--- Fast mode ---
5 1L inc PC
1H ALU-in1 = DB
2L inc PC ALU-in2 = Y
2H ADT-H = DB
3L ADT-L = ALU-out
ACTION = Carry
if ACTION inc ADT-H
3H AC/X = DB
4L adjust ST-flags
inc PC
BA TSX 2 1L inc PC X = SP
1H -
2L -
--- Fast mode ---
1 1L inc PC X = SP
BB Unknown
BC LDY $xxxx,X
BD LDA $xxxx,X
5 1L inc PC
1H ALU-in1 = DB
2L inc PC ALU-in2 = X
2H ADT-H = DB
3L ADT-L = ALU-out
ACTION = Carry
3H AC/Y = DB
4L adjust ST-flags
if no ACTION enable PC
if ACTION inc ADT-H
4H AC/Y = DB
5L adjust ST-flags
inc PC
--- Fast mode ---
5 1L inc PC
1H ALU-in1 = DB
2L inc PC ALU-in2 = X
2H ADT-H = DB
3L ADT-L = ALU-out
ACTION = Carry
if ACTION inc ADT-H
3H AC/Y = DB
4L adjust ST-flags
inc PC
BE see $B9
BF Unknown
C0 CPY #$xx
C9 CMP #$xx
E0 CPX #$xx
2 1L inc PC Y/AC/X -> ALU-in2
1H ALU-in1 = DB
2L inc PC
adjust ST-flags
C1 CMP ($xx,X)
6 1L inc PC ALU-in1 = X
1H ALU-in2 = DB
ADT-L = DB
2L enable ADT
2H ADT-L = ALU-out
3L disable ADT-load
3H ADT-L-l = DB
4L inc ADT-L
4H ADT-H = DB
5L enable ADT-load ALU-in1 = AC
5H ALU-in2 = DB
6L inc PC
adjust ST-flags
--- Fast mode ---
5 1L inc PC ALU-in1 = X
1H ALU-in2 = DB
2L enable ADT ADT-L = ALU-out
2H disable ADT-load ADT-L-l = DB
3L inc ADT-L
3H ADT-H-l = DB
4L enable ADT-load ALU-in1 = AC
4H ALU-in2 = DB
5L inc PC
adjust ST-flags
C2 Unknown
C3 Unknown
C4 CPY $xx
C5 CMP $xx
E4 CPX $xx
3 1L inc PC
1H ADT-L = DB
2L enable ADT Y/AC/X -> ALU-in2
2H ALU-in2 = DB
3L inc PC
adjust ST-flags
C6 DEC $xx
E6 INC $xx
5 1L inc PC
1H ADT-L = DB
2L enable ADT
2H disable ALU ALU-in1 = DB
3L -
3H DB-out DB = ALU-out
4L activate ALU
4H DB = ALU-out
5L inc PC
adjust ST-flags
--- Fast mode ---
4 1L inc PC
1H ADT-L = DB
2L enable ADT
2H ALU-in1 = DB
3L -
3H DB-out DB = ALU-out
4L inc PC
adjust ST-flags
C7 Unknown
C8 see $88
C9 see $C0
CA DEX
E8 INX
2 1L inc PC ALU = X
1H X = ALU
2L -
CB Unknown
CC CPY $xxxx
CD CMP $xxxx
EC CPX $xxxx
4 1L inc PC
1H ADT-L = DB
2L inc PC
2H ADT-H = DB
3L enable ADT Y/ALU-in1 = AC
3H ALU-in2 = DB
4L inc PC
adjust ST-flags
CE DEC $xxxx
EE INC $xxxx
6 1L inc PC
1H ADT-L = DB
2L inc PC
2H ADT-H = DB
3L enable ADT
3H disable ALU ALU-in1 = DB
4L -
4H DB-out DB = ALU-out
5L activate ALU
5H DB = ALU-out
6L inc PC
DB-in
--- Fast mode ---
6 1L inc PC
1H ADT-L = DB
2L inc PC
2H ADT-H = DB
3L enable ADT
3H ALU-in1 = DB
4L -
4H DB-out DB = ALU-out
5L inc PC
DB-in
CF Unknown
D0 see $10
D1 CMP ($xx),Y
5+ 1L inc PC
1H ADT-L = DB
2L disable ADT-load
disable ADT-C
enable ADT
2H ALU-in2 = DB
3L inc ADT-L ALU-in1 = Y
3H ADT-H-l = DB
4L ena. ADT-load(L) ADT-L = ALU-out
ACTION = Carry
4H ena. ALU-inAC ALU-in1 = DB
5L inc PC
adjust ST-flags
if no ACTION enable PC
if ACTION inc ADT-H
5H ALU-in1 = DB
6L adjust ST-flags
--- Fast mode ---
5 1L inc PC
1H ADT-L = DB
2L disable ADT-load
disable ADT-C
enable ADT
2H ALU-in2 = DB
3L inc ADT-L ALU-in1 = Y
3H ADT-H-l = DB
4L ena. ADT-load(L) ADT-L = ALU-out
ACTION = Carry
if ACTION inc ADT-H
4H ena. ALU-inAC ALU-in1 = DB
5L inc PC
adjust ST-flags
D2 Unknown
D3 Unknown
D4 Unknown
D5 CMP $xx,X 4 1L inc PC ALU-in2 = X
1H ALU-in1 = DB
ADT-L = DB
2L enable ADT
2H -
3L ADT-L = ALU-out
3H ena. ALU-inAC ALU-in1 = DB
4L inc PC
adjust ST-flags
--- Fast mode ---
3 1L inc PC ALU-in2 = X
1H ALU-in1 = DB
2L enable ADT ADT-L = ALU-out
2H ena. ALU-inAC ALU-in1 = DB
3L inc PC
adjust ST-flags
D6 DEC $xx,X
F6 INC $xx,X
6 1L inc PC ALU-in2 = X
1H ALU-in1 = DB
ADT-L = DB
2L enable ADT
2H -
3L ADT-L = ALU-out
3H disable ALU ALU-in1 = DB
4L -
4H DB-out DB = ALU-out
5L activate ALU
5H DB = ALU-out
6L inc PC
adjust ST-flags
--- Fast mode ---
4 1L inc PC ALU-in2 = X
1H ALU-in1 = DB
2L enable ADT ADT-L = ALU-out
2H ALU-in1 = DB
3L -
3H DB-out AC = ALU-out
4L inc PC
adjust ST-flags
D7 Unknown
D8 see $18
D9 CMP $xxxx,Y
DD CMP $xxxx,X
4+ 1L inc PC
1H ALU-in1 = DB
2L inc PC ALU-in2 = Y/X
2H ADT-H = DB
3L ADT-L = ALU-out
ACTION = Carry
3H ena. ALU-inAC ALU-in1 = DB
4L inc PC AC = ALU-out
if no ACTION enable PC
if ACTION inc ADT-H
4H ALU-in1 = DB
5L adjust ST-flags AC = ALU-out
--- Fast mode ---
4 1L inc PC
1H ALU-in1 = DB
2L inc PC ALU-in2 = Y/X
2H ADT-H = DB
3L ADT-L = ALU-out
ACTION = Carry
if ACTION inc ADT-H
3H ena. ALU-inAC ALU-in1 = DB
4L inc PC AC = ALU-out
adjust ST-flags
DA Unknown
DB Unknown
DC Unknown
DD see $D9
DE DEC $xxxx,X
FE INC $xxxx,X
7 1L inc PC
1H ALU-in1 = DB
2L inc PC ALU-in2 = Y
2H ADT-H = DB
3L ADT-L = ALU-out
ACTION = Carry
3H disable ALU ALU-in1 = DB
4L inc PC
if no ACTION enable PC
if ACTION inc ADT-H
4H ALU-in1 = DB
5L -
5H DB-out DB = ALU-out
6L activate ALU
6H DB = ALU-out
7L inc PC
adjust ST-flags
--- Fast mode ---
5 1L inc PC
1H ALU-in1 = DB
2L inc PC ALU-in2 = Y
2H ADT-H = DB
3L ADT-L = ALU-out
ACTION = Carry
if ACTION inc ADT-H
3H ALU-in1 = DB
4L -
4H DB-out DB = ALU-out
5L inc PC
adjust ST-flags
DF Unknown
E0 see $C0
E1 see $01
E2 Unknown
E3 Unknown
E4 see $C4
E5 see $05
E6 see $C6
E7 Unknown
E8 see $CA
E9 see $09
EA NOP 2 1L inc PC
1H -
2L -
--- Fast mode ---
1 1L inc PC
EB Unknown
EC see $CC
ED see $0D
EE see $CE
EF Unknown
F0 see $10
F1 see $11
F2 Unknown
F3 Unknown
F4 Unknown
F5 see $15
F6 see $D6
F7 Unknown
F8 see $18
F9 see $19
FA Unknown
FB Unknown
FC Unknown
FD see $1D
FE see $DE
FF Unknown
Schematics
My TTL-6502 as Eagle schematics and as PNG files, zipped of course.Homebuilt CPUs WebRing
Join the ring?
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