Build your own 6502
What is it?
The original idea of this project was to build the well known 6502 processor using only normal available TTL IC's. Unfortunately this turned out to be quite impossible seen from a practical view of point. An explanation will follow.Dividing the 6502 in blocks
There is no schematic of the interior of the 6502 available (AFAIK), so I had to make my own based on the "internal architecture of 6501" published in many datasheets and based on how the 6502 behaves when executing commands. First I divided the 6502 into functional blocks:- CPU in/output
- Instruction decoder
- Program Counter
- Temporary Counter
- Buffer
- Registers A, X and Y
- Static Addresses
- Stackpointer
- Flag register
- ALU
- Address adder
CPU in/output
This part is the actual interface to the outside world. IC84, 6502DEBUG, represents the 40 pins that should replace the 6502 when you really want to test/use the self-built processor.As you can see PHI1 is created by inverting PHI0. PHI2 is created by inverting PHI1 on its turn. Why not using PHI0 as source for PHI2? At this moment I use my experience gathered with my project <<<<02to816>>>>. A real prototype can confirm whether I was wrong or not.
Two 573's, IC81 and IC82, latch and buffer the address lines. I need the latch function as in certainly one occasion, TSX, I need the internal address bus temporarily for other things.
Two 573's, IC44 and IC86, buffer the data lines. IC86 buffers the data towards the 6502. IC86 is clocked by PHI2 so the 6502 also has access to the data when the original data has disappeared already. Its Output-Enable is steered by the Instruction decoder. IC44 is clocked by the Instruction decoder. Its Output-Enable is steered by I24 through IC85a (32: quad 2-input OR).
A 125 buffers the R/W-line which is I26. But I'm thinking about using I24 here as well.
As you can see, all outgoing buffers can be tri-stated. This is not a normal feature of the 6502. But some Atari computers have a 6502 clone aboard that can tri-state. I also want to mention the 6510 (C64), 8501(C16 and Plus/4) and 8502 (C128), which have this feature as well.
Instruction-decoder
The instruction decoder is that part of the 6502 which decides what element should be activated at a given time for a certain instruction. Some instructions need more then one cycle to be performed due to the fact that to complete it, data has to be read or written to the world outside the 6502. For example, the command LDA ($56),Y performs four other reads beside the original read of the opcode.We first have to decide what the actual decoder needs as input. My thoughts:
- Opcode: the 6502 opcode is 8 bits wide.
- Counter: a counter is used to count the steps of every instruction. AFAIK instructions do not need more then 7 clock cycles ie. this means three bits plus one for the original clock should be enough.
- The original clock signal, PHI0. This means that every count is divided in two steps: 0L, 0H, 1L, 1H etc. etc.
- Branch: branches need some extra information whether a branch should be taken or not, one bit.
- We need one bit to tell the decoder that there is an Interrupt, Reset etc. going on. The actual information what special operation, read: instruction, has to be executed, can be found at the lines normally reserved for the data bits.
Opcode:
IC48 (573: 8 bits latch) latches the data coming from the external data bus at the falling edge of PHI0 at count 0.
Counter:
IC45a (393: 4 bits binary counter with clear) is the counter inside the decoder. At every falling edge of PHI0 the output is increased by one. IC46a (27: 3-input NOR) generates the needed clock pulse for IC48 by NOR-ing the first three outputs of the 393. PHI0 is not needed here as count 0L actually does not exist.
Decoder:
As said, the originally idea was to build the 6502 only using TTL-IC's of the 74xxx series. Then I started to calculate the Boolean equations for every element in each functional block. The results were not nice looking at all. For example, the input for incrementing the Program Counter alone needed an AND-gate with more then 41 inputs! Most probably the designers of the 6502 did use this method but there is a big difference in creating a 41-input AND-gate directly in silicon or cascading several normal TTL IC's. Not wanting to use fast programmable arrays like PAL's, CPLD's or equivalents, I decided to use EPROM's.
I did not think of using EPROM's in the first place because of the access-time, 150-300 ns. compared to 5-10 ns, and the glitches in the output. But then I realised that the access time was not a problem at all for a 1 MHz version. And the problem of the glitches in the output could be solved by using a latch and creating a circuit that generates the needed pulse for the latch.
Will there be differences with the original 6502? Yes, of course! Normally the R/W-line will change state within the first 150 ns. after the falling edge of PHI2. Now this will depend on the access time of the used EPROM's.
Pulse generator:
The main idea is to latch the output of the EPROM after it had enough time to become stable, read: access time. One half of 221 (dual mono-stable multivibrator), IC63a, takes care of the positive edge of PHI0, IC63B takes care of the falling edge. Both halves output a pulse at the appropriate occasion that is as long as the needed access time. Both pulse are OR-ed by IC85d (32: 2-input OR) and fed to IC69a, another 221 half. IC69a outputs the needed pulse for all the decoding EPROM's.
What kind of EPROM do we need?
At this moment I think I only need 14 bits as input meaning we can use 27128's or equivalents for the job. In the schematic I used 27256s as you can see. The reason for this šs that if I ever find out that I need an extra bit, I don't have to change the whole schematic :)
Resetting the decoder:
The idea is that at phase H of the last cycle output I20 is set. I20 is OR-ed by IC85c with the signal coming from the Reset-flipflop (see later) and AND-ed by IC47b with PHI0. So the moment I20 is set, the 393 is cleared and we automatically enter step 0H. The moment PHI0 becomes (L), the CLR input becomes (L) as well.
At step 0H actually nothing can happen any more as the EPROM's already have been latched. And just FYI, step 0L even doesn't exist at all! One important thing: the first that has to be done at step 1L is resetting I20 otherwise our TTL6502 definitively stops working. Find out yourself why.
IC46a (27: triple 3-input NOR) NORs the first three outputs of the 393. At count 0H its output becomes (H). This signal is used to latch the state of the IRQ, NMI, Reset and the opcode.
Reset:
The resetline is used as clock signal for IC42a (74: dual data flipflop). The moment the resetline becomes (H), the Q-output is set. First this output is OR-ed by IC85C with I82. The rest is described in "Resetting the decoder".
Secondly this Q-output is NOR-ed by IC46c (27: triple 3-input NOR) with the latched NMI- and IRQ-signal. The use of this NOR gate is discussed later.
Third this signal serves as one of the inputs of IC51 (573: 8-bits latch).
NMI:
After inverting it first, the NMI line is used as clock signal for IC43a (74: dual data flipflop). The moment the NMI line becomes (H), the Q-output is fed to IC46c, see "Reset", and to IC51, see later.
IRQ:
The IRQ signal is OR-ed by IC68a (32: quad 2-input OR) with the Interrupt disable bit. The output of this OR gate goes to IC46c and IC51.
IC46c and IC51
The output of IC46c, the 3-input NOR gate that NORs Reset, NMI and IRQ, signals that one or more of these signals is active. This signal is latched into IC43b (74: dual data flipflop) which on its turn is responsible for either enabling IC48, the 573 that latches the opcode, or IC51, the 573 that latches Reset, NMI and IRQ.
RDY:
The original idea was using IC42b (74: dual data flipflop) for latching the RDY signal and OR-ing it (IC85b) with the original PHI0. But I was unsure if the delay time of IC42b could cause a glitch in the output of IC85b. The original datasheets mention that RDY must be (L) at least a 125 ns. before the falling edge of PHI2 to be recognised as so. As I had one 221 half left over, I decided to create a rising edge for IC42b about 100 ns. before the falling edge of PHI2. In this way I was sure of a stable (H) coming out of IC85b at the falling edge of PHI2.
The Program Counter / Temporary Counter
Both parts are exactly the same, the only difference is the way that they are used. What the PC, should be known IMHO. The TC is used with instructions using indirect addressing like LDA ($xx),Y. The PC is takes care of the address bus the moment the data on the addresses $00xx and $00xx+1 is read. This data is stored into the TC which then is used in turn to read the address at $00xx/$00xx+1.The heart of PC/TC are four cascaded 191's, a pre-loadable 4-bits binary up/down counter. Here it is only used in the "up" mode. As both counters are connected to the outgoing address bus and both have no tri-state capabilities, two 541's are added to provide this function.
At this moment both counters have a separate Load-input for the low- and high-byte. IMHO there is a good chance that I can combine them to one input, we'll see.
Buffers
In case of a a jump or a branch the new address has to be stored somewhere, in this case two 573's, IC20 and IC21, are used. The inputs are connected to the internal data bus, the outputs to the "buffer address bus" which leads to the inputs of the 191's mentioned above.The third part of the "Buffer" are IC57 and IC02, both 541's. These buffers are used to store the Program counter on the stack and to copy the stackpointer to register X.
The Registers A, X and Y
This part is easy to describe: three 573's, IC36, IC41 and IC56, serve as register A, X and Y. The inputs as well as the outputs are connected to the internal data bus.The Static addresses
When reading something from the Stack, the Stack Pointer only provides the address lines A0 to A7; A8 to A15 must be $01 and is provided by the 6502 itself.After a reset, the address $FFFC has to be generated in some way. The same has to happen when a NMI or IRQ occurs.
IC35 and IC36, two 27256 EPROM's, provide the needed addresses. They are fed with the same signals as the EPROM's of the Instruction decode. For the few addresses they have to provide, this sure is an overkill. An earlier solution was the use of some 541's and 244's which inputs were wired according the needed addresses. But this solution is simpler and also more flexible.
The Stackpointer
You will notice that the hardware of the SP has the same setup as the one of the PC. But as there are only 8 bits needed, only half of the amount is used. The SP gets its input from the internal data bus. Its outputs are connected to the buffer address bus. In case the Stack has to be addressed, the output of the SP is plus the well known $01 higbyte are stored in the temporary counter and then put on to external address bus.The Flag register
The core of the Flag register (FR) is made out of seven 74's; dual data flipflops. With the exception of IC66B, the Preset- and Clear-input are all tied to Vcc so they only can be (re-)set on command of the Instruction decoder through the internal data bus. The exception, IC66b, handles Overflow and that can be set by the SO-input.The FR gets its data from the internal data bus. This is either data resulting from a memory move (PLP) or an update of one or more arithmetical bits (Zero, Carry, Overflow, Negative). The Negative bit has to be (re-)set the moment the data is placed on the data bus. The other three bits have to be (re-)set during the next step.
In eight cases the state of a particular bit is needed to decide whether a branch should be taken or not. Both outputs of a 74 are each OR-ed with a signal coming from the Instruction decoder. The idea is that the ID resets the needed bit according the type of branch. Take for example BEQ: if the Zerobit is set, Q\ of IC64b is (L). Resetting I72 means that the output of IC76a (32: quad 2-input OR) becomes (L) as well. This on its turn causes the output of IC83 (30: 8-input NAND) to become (H) which on its turn informs the ID what the next steps should be.
The ALU
The ALU would have not been a problem if the 6502 had no decimal mode. But it has and the ALU-IC's I'm familiar with cannot deal with this mode so I had to use EPROM's here as well. But in this case these have to be fast ones as I need to cascade two in a row! The reason they have to be fast is that the total needed time to make a calculation is the sum of the access time of both EPROM's because the second EPROM has to wait for an eventual Carry and/or Zero of the first one.The reason for cascading the EPROM's is that each one handles only 4 bits of each operand. That makes 8 bits together. Then it needs to be able to handle at least the next commands:
- ADC
- AND
- ASL
- BIT
- CMP / CPX / CPY
- DEC / DEX / DEY
- EOR
- INC / INX / INY
- LSR
- ORA
- ROL
- ROR
- SBC
Each EPROM outputs 4 databits, a Carry, an Overflow and a Zero; that leaves one bit unused. The overflow of the first EPROM is not used of course.
The first operand to be processed is stored in IC61, a 573. The second operand is always provided by an register or will come from the external data bus and therefore already is latched in one or another way and so doesn't need a latch of its own.
As IC61 doesn't have to share its output with another IC, only clocking is needed.
I also play with the idea to implement the core of the 65C02 and that CPU has more commands. This could mean I have to choose for a 27512 in the future. A fact is that having the Decimal flag its own input is a waist of memory as only ADC and SBC are influenced by it (AFAIK). Another idea is to feed the ID-EPROM controlling the ALU with the Decimal flag; there is still one line left, remember? This means on its turn that we can expand the ALU up to 32 commands using the same EPROM and still have the 27512 in reserve.
The Address adder
The initial design contained a 4-EPROM ALU that could be used to calculate addresses as well. But realising that I even for the 1 MHz. version I needed real fast EPROM's, I decided to drop this idea and to make a separate adder for addresses only.The basic idea is quit simple: four cascaded 83's (4 bits full adders) do the trick. But because they don't have tri-state outputs, two 573's are added to complete the design.
The internal address bus, the data bus and an AND gate, IC47c, provide the inputs for the 83's. IC47a (08: quad 2-input AND) provides the data for ALL inputs of the high byte of the second operand. The idea is that, with one exception, a Zero plus an eventual Carry is added to the highbyte of the address. The exception is a negative branch. A branch is negative if bit 7 of the data bus is (H). I6 makes sure that the highbyte remains $00 in all other cases.
The data bus provides the data both for the first and second operand. The second operand comes from IC61 which provides the data for the ALU as well. Two 573's buffer the data bus, two 541's the internal address bus.
I have been thinking about combining the above designs ie. cascading two EPROM's and two 83's. It would differ two IC's. The main reason not to do it is that I have some doubts about the two cascaded EPROM's. In case of an Y-indexed indirect instruction, 'opc ($xx),Y, I have less then a half cycle to output the address. And that makes things critical. The data operations I know so far, are less time critical.
Used IC's
Code: type: XY-coord.: ----- ------- ---------- IC01 74AS573 IC02 74AS573 IC03 74AS573 IC10 74LS191 IC11 74LS191 IC12 74LS541 IC13 74LS541 E1 IC14 74LS191 IC15 74LS191 IC16 74LS191 IC17 74LS191 IC18 74LS541 IC19 74LS541 IC20 74AS573 IC21 74AS573 IC22 27256 IC23 27256 IC24 74AS573 IC25 27256 IC26 74AS573 IC28 74AS573 IC30 74LS541 IC32 74LS83 IC33 74LS191 IC34 74LS191 IC35 27256 IC36 27256 IC37 74LS541 IC38 74AS573 IC39 74AS573 IC40 74ALS04 xx xx xx C1 IC41 74AS573 IC42 74LS74 IC43 74LS74 IC44 74AS573 IC45 74LS393 IC46 74LS27 IC47 74LS08 IC48 74AS573 IC49 27256 IC50 74AS573 IC51 74AS573 IC52 74AS573 IC53 27256 IC54 74AS573 IC55 27256 IC56 74AS573 IC57 74AS573 IC58 27256 IC59 27256 IC60 74AS573 IC61 74AS573 IC63 74LS221 IC64 74LS74 IC65 74LS74 IC66 74LS74 IC67 74LS74 IC68 74LS32 IC69 74LS221 IC70 27256 IC71 74AS573 IC72 27256 IC73 74AS573 IC74 27256 IC75 74AS573 IC76 74LS32 IC78 74LS541 IC81 74AS573 C1 IC82 74AS573 C2 IC83 74LS30 IC84 6502 B2 IC85 74LS32 IC86 74AS573 IC87 74LS83 IC88 74LS83 IC91 74LS83 IC92 74LS125 IC93 74LS191 F1 IC94 74LS191 F2
All outputs of the Instruction decoder
I00 IC61 11 C Clocking 1st byte from int. data bus towards ALU (H)
I01 IC02 1 OC Enable LB int. address bus towards int. data bus (L)
I02 IC25 11 C Clocking LB from Adder towards Temp. address bus (H)
IC24 11 C Clocking HB from Adder towards Temp. address bus
I03 IC25 1 OC Enabling LB from Adder towards Temp. address bus (L)
I04 IC24 1 OC Enabling HB from Adder towards Temp. address bus
I05
I06 IC71 13 7Q Enabling bit 7 towards HB 2nd operand Adder (H)
I07 IC68 4 I0 Check if Carry is reset (L)
I08 IC64 3 CLK Clock bit 0 data bus into Carry flipflop (/)
I09 IC68 10 I1 Check if Carry is set (L)
I10 IC68 12 I0 Check if Zero is reset (L)
I11 IC64 11 CLK Clock bit 1 data bus into Zero flipflop (/)
I12 IC68 2 I1 Check if Zero is set (L)
I13 IC35 22 OE Enable output LB Static addresses (L)
I14 IC36 22 OE Enable output HB Static addresses (L)
I15 IC02 11 C Clock LB int. address bus towards int. data bus (H)
IC57 11 C Clock HB int. address bus towards int. data bus
I16 IC76 2 I1 Check if Negative is set (L)
I17 IC30 1 G1 Enable result ALU towards int. data bus (L)
I18 IC78 1 G1 Enable output Flag register towards int. data bus (L)
I19 IC47a 1 emulate SYNC during PHI0 = H (H)
I20 IC85 10 I1 Clearing 393 counter (H)
I21 IC42 1 CLR Clearing Reset flipflop IC42a (L)
I22 IC43 1 CLR Clearing NMI flipflop IC43a (L)
I23 IC92 10 OE Enable flags ALU towards int. data bus (L)
I24 IC85 1 I0 Enabling 573 towards external data bus via OR (L)
I25 IC44 11 C Clocking data into 573 towards external data bus (H)
I26 IC92 2 I R/W-line
I27 IC81 11 C Clocking address to external address bus (H)
IC82 11 C
I28 IC12 1 G1 Enabling address PC towards internal address bus (L)
IC13 1 G1
I29 IC86 1 OC Enabling data 573 towards internal data bus (L)
I30 IC93 14 CLK Increase address Program Counter (\)
I31 IC93 11 LD Load LB PC with new address from temp. address bus (L)
IC94 11 LD
I32 IC10 11 LD Load HB PC with new address from temp. address bus (L)
IC11 11 LD
I33 IC18 1 G1 Enabling address TC towards internal address bus (L)
IC19 1 G1
I34 IC14 14 CLK Increase address Temporary Counter (\)
I35 IC14 11 LD Load LB TC with new address from temp. address bus (L)
IC15 11 LD
I36 IC16 11 LD Load HB TC with new address from temp. address bus (L)
IC17 11 LD
I37 IC57 1 OE Enable HB int. address bus towards int. data bus (L)
I38 IC20 11 C Clocking data into 573 towards LB temp. data bus (H)
IC01 11 C Clocking data into 573 towards LB Address adder (H)
I39 IC20 1 OC Enabling 573 towards LB temp. data bus (L)
I40 IC21 11 C Clocking data into 573 towards HB temp. data bus (H)
IC03 11 C Clocking data into 573 towards HB Address adder (H)
I41 IC21 1 OC Enabling 573 towards HB temp. data bus (L)
I42 IC37 1 G1 Enable Stackpointer towards temp. address bus (L)
I43 IC65 11 CLK Clock bit 3 data bus into Decimal flipflop (/)
I44 IC66 3 CLK Clock bit 4 data bus into Break flipflop (/)
I45 IC76 4 I0 Check if Overflow is reset (L)
I46 IC66 11 CLK Clock bit 6 data bus into Overflow flipflop (/)
I47 IC33 5 D/U\ Counting Stackpointer up (H) or down (L)
I48 IC33 14 CLK In/decrease Stackpointer (\)
I49 IC33 11 LD Load Stackpointer with address from int. data bus (L)
IC34 11 LD
I50 IC38 11 C Clock data internal data bus into register A (H)
I51 IC38 1 OC Enable data register A towards internal data bus (L)
I52 IC41 11 C Clock data internal data bus into register X (H)
I53 IC41 1 OC Enable data register X towards internal data bus (L)
I54 IC56 11 C Clock data internal data bus into register Y (H)
I55 IC56 1 OC Enable data register Y towards internal data bus (L)
I56 IC65 3 CLK Clock bit 2 data bus into IRQ disable flipflop (/)
I57 IC22 23 A11 ALU operator bit 0
IC23 23 A11
I58 IC22 2 A12 ALU operator bit 1
IC23 2 A12
I59 IC22 26 A13 ALU operator bit 2
IC23 26 A13
I60 IC22 27 A14 ALU operator bit 3
IC23 27 A14
I61 IC76 12 I0 Check if Negative is reset (L)
I62 IC67 3 CLK Clock bit 7 data bus into Negative flipflop (/)
I63 IC76 10 I1 Check if Overflow is set (L)
All instructions step by step
About illegal opcodes: I have proof that the illegal opcodes are the rest product of the legal instructions. I first will implement these legal ones and then see if I can set up things so that the illegal opcodes pop up by themselves.About the Reset sequence: stepping through a reset sequence, I noticed that it does something like handling an Interrupt. IMHO it is combination of clearing the Break and saving gates by using partly the Interrupt handling.
The last step of an instruction (H), the one before (xL) and the first step (1L) perform some operations which generally are the same for all instructions
Code Opcode Cycli Step Action Use of int. bus
* ALL xL Valid for ALL opcodes
I15 = H clock-input IC02 and IC57 = (H)
I26 = H read, R/W = (H)
I27 = H enable clock 573's -> ext. address bus
I28 = L enable PC towards int. address bus
I29 = H disable data towards int. data bus
* ALL xH Valid for ALL opcodes
I13 = H disable Static address EPROM's
I14 = H
I15 = L buffers IC02 and IC57 store address PC
I20 = H set clear for 393 counter
I29 = L enable data towards int. data bus
I30 = H clock-input Program Counter = (H)
* ALL 1L Valid for ALL opcodes
I20 = H reset clear for 393 counter
I30 = L (\) increment Program counter
Ixx = L for CLK input of all Flag flipflops
* 1xx RESET 1L Just freeze the busses
I20 = H reset clear for 393 counter
I24 = H disable data towards ext. data bus
I25 = H disable clock 573 ext. data bus
I26 = H R/W = (H)
I27 = L disable clock 573's ext. address bus
I29 = H disable data towards int. data bus
all other Ixx are set inactive
1H Same as 1L
2L Output the reset address $FFFC on the bus
I13 = L Static address EPROM's output $FFFC
I14 = L
I27 = H enable clock 573's ext. address bus
I33 = L enable TC towards int. address bus
I34 = H clock-input Temp. Counter = (H)
I35 = L enable load LB Temp. Counter
I36 = L enable load HB Temp. Counter
2H Wait for first byte
I29 = L enable data towards int. data bus
I35 = H disable load LB Temp. Counter
I36 = H disable load HB Temp. Counter
I38 = H enable clk IC20 -> LB temp. addr. bus
3L Process byte, increase address
I13 = H disable Static address EPROM's
I14 = H
I34 = L (\) causes TC to increase address
I38 = L disable clk IC20 -> LB temp. addr. bus
3H Wait for second byte
I31 = L enable load LB Program Counter
I32 = L enable load HB Program Counter
I34 = H clock-input Temp. Counter = (H)
I39 = L enable data IC20 -> LB temp. addr. bus
I40 = H enable clk HB IC21 -> temp. addr. bus
I41 = L enable data IC21 -> temp. addr. bus
4L Process byte
I13 = L enable LB Static address EPROM $04
I28 = L enable PC towards int. address bus
I31 = H disable load LB Program Counter
I32 = H disable load HB Program Counter
I33 = H disable TC towards int. address bus
I40 = L clock data into IC21 (573)
4H Reset Break, rest according xH
I44 = H (/) clocks 0 into Break flag
* 01x NMI 1L Prepare to write HB Program counter to Stack
I14 = L HB Static address EPROM outputs $01
I24 = L enable data towards ext. data bus
I26 = H write, R/W = (L)
I29 = H disable data towards int. data bus
I33 = L enable TC towards int. address bus
I34 = H clock-input Temp. Counter = (H) I35 = L enable load LB Temp. Counter
I36 = L enable load HB Temp. Counter
I37 = L enable HB address towards int. data bus
I42 = L Stackpointer outputs address
1H Write and prepare SP for next store
I47 = H Stackpointer will count down
I48 = H clock-input Stackpointer = (H)
2L Prepare to write LB Program counter to Stack
I01 = L enable LB address towards int. data bus
I37 = H disable HB address towards int. data bus
I48 = L (\) causes Stackpointer to decrease
2H Write and prepare SP for next store
I48 = H clock-input Stackpointer = (H)
3L Prepare to write Flag register to Stack
I01 = H disable LB address towards int. data bus
I18 = L enable Flag reg. towards int. data bus
I48 = L (\) causes Stackpointer to decrease
3H Write and prepare SP to point to next address
I48 = H clock-input Stackpointer = (H)
4L Output the NMI address $FFFA on the bus
I13 = L Static address EPROM's output $FFFA
I14 = L
I48 = L (\) causes Stackpointer to decrease
4H Wait for first byte
I48 = H clock-input Stackpointer = (H)
Rest is same as step 2H Reset
5L Same as step 3L Reset
5H Same as step 3H Reset
6L Same as step 4L Reset
6H Reset Break, set Int. disable, rest accord. xH
I44 = H (/) clocks 0 into Break flag
I56 = H (/) clocks 1 into Int. disable flag
* 001 IRQ Same as NMI except address $FFFE is outputted
00 BRK Same as IRQ except Break is set
01 ORA ($xx,X)
21 AND ($xx,X)
41 EOR ($xx,X)
61 ADC ($xx,X)
E1 SBC ($xx,X)
6 1L Store X in 2nd operand Address adder
I00 = H store data into ALU/Adder buffer
I30 = L (\) increment Program counter
I53 = L enable X register towards int. data bus
1H Read Zeropage address
I00 = L disable store data into ALU buffer
I02 = H store data into Adder output buffer
I14 = L HB Static address EPROM outputs $00
I29 = L enable data towards int. data bus
I30 = H clock-input Program counter = (H)
I34 = H clock-input Temp. Counter = (H)
I35 = L enable load LB Temp. Counter
I36 = L enable load HB Temp. Counter
I38 = H clock data IC20 -> LB temp. addr. bus
I39 = L enable data IC20 -> LB temp. addr. bus
I53 = H disable X register towards int. data bus
2L Output result Adder -> TC -> int. address bus
I02 = L disable store data Adder output buffer
I03 = L enable LB Adder output buffer
I14 = H disable HB Static address EPROM output
I28 = H disable PC towards int. address bus
I30 = L (\) increment Program counter
I33 = L enable TC towards int. address bus
I39 = H disable data IC20 -> LB temp. addr. bus
2H Read 1st address byte
I30 = H clock-input Program counter = (H)
I35 = H disable load LB Temp. Counter
I36 = H disable load HB Temp. Counter
3L Prepare for next byte
I03 = H disable LB Adder output buffer
I34 = L (\) causes TC to increase address
I38 = L disable clk data IC20
3H Read 2nd address byte
I30 = H clock-input Program counter = (H)
I39 = L enable data IC20 -> LB temp. addr. bus
I40 = H clock data IC21 -> HB temp. addr. bus
I41 = L enable data IC21 -> HB temp. addr. bus
4L Output address, copy Accu to 1st operand
I00 = H store data into ALU/Adder buffer
I29 = H disable data towards int. data bus
I51 = L enable register A towards int. data bus
I35 = L enable load LB Temp. Counter
I36 = L enable load HB Temp. Counter
I40 = L disable clk data IC201
4H Read byte to be processed
I00 = L disable store data ALU/Adder buffer
I29 = L enable data towards int. data bus
I51 = H disable register A towards int. data bus
I35 = H disable load LB Temp. Counter
I36 = H disable load HB Temp. Counter
I57..60 set according operation for ALU
5L Copy result to A
I17 = L enable result ALU towards int. data bus
I29 = H disable data towards int. data bus
I50 = H store data into register A
5H Copy bit 7 to Negative. flag
I17 = H disable result ALU towards int. data bus
I23 = L enable Carry etc. towards int. data bus
I50 = L disable store data into register A
I62 = H (/) clk bit 7 to Negative flag
5L Copy Zero to Zero flag
I11 = H (/) clk ALU Zero to Zero flag
I23 = H disable Carry etc. towards int. data bus
6H See xH
02 Unknown
03 Unknown
04 Unknown
.
.
.
Lost due to a crash ???
.
.
.
Hardware
Bus:
Power 8
Opcode 8
Counter 3
Clock 1
BraD 1
RinD 1
Internal data bus 8
Address bus 16
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46
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