Build your own Memory Management Unit
What is it
Read the page about the 74LS612 MMU first to find out what a MMU is and does. This schematic enables you to build your own MMU.
The story
After designing the PC-Card I decided to make a version for 6502 based computers. This design enabled the user to expand his computer to 16 MB using a 65816, a 74LS612 MMU or both. Unfortunately I found out that both IC's are hardly available. So I decided to design a MMU using normal available IC's.The design
The core of the 74LS612 is made of sixteen 12-bit wide registers. The idea rose to use two 20 ns 2K*8 cache-SRAMs. The delay of 20 ns is not critical as the build-up of the address is somewhere halfway the lower half of PHI2.Having 16 bits to our proposal means we can do more with this design then with the 74LS612. Using four more addresslines means we could expand up to 256 MB! On the other hand it gives us the opportunity to reduce the size of the individual pages. Using the 74LS612 the size of a page is 4 KB. My idea is to add two other lines to reduce them to 1 KB.
Why 1 KB? The total I/O area of the PC is just 1 KB big. The Video-RAM of the CBM/PET is just 1 KB. The text-only video-RAM of the PC, 2KB, and I/O-area could fit neatly in the $8xxx-area not used by the CBM/PET.
Next thing to cover is the output of our MMU. The output is either the original lines or the programmed ones. 257A's are used to switch between them. When in "original mode", A16..23 become (L). The 257A enables you to tristate the MMU if needed.
The input-side uses the same idea: in "original mode" the addressline A0..A5 are connected to the SRAMs, in "MMU-mode" the addresslines A10..15 are.
The controllines OE and CS are tied together. In "original mode" they are activated when the MMU is selected. In "MMU-mode" they are activated all the time.
The WE-input is hold (H) during the "MMU-mode" ensuring the SRAMs output their contents all the time. In "original mode" they are connected with the CPU's R/W-line.
How to handle 16 input lines.
The chance is quit big you will use this MMU with an 8-bit CPU. The 12-bit wide databus of the 74LS612 proved to be a problem. Andre Fachat's GECKO only uses 8 bits but the penalty is he only can address up to 1 MB.
I got rid of this problem by using an extra addressline and a 139 demultiplexer to be able to handle each SRAM separately through a 245 buffer. The 139 also provided a neat way to disable these buffers when in "MMU-mode".
Schematics
This MMU has the same connections as the already mentioned 74LS612 MMU. But how does it work?When the MMU is not active, ie. the input /MM
Expanding the design
Multiple configurations.Only needing 6 of the 11 addresslines of the 2K RAMs means that the rest has to be tied to GND. Or..... Connecting these lines to a latch means we can store multiple configurations. Instead of giving up to 128 commands to to change from one configuration to another, just one will do. OK, the configurations have to be stored in the MMU first but that is the only time you need to apply so many MMU commands in row. For the rest it is just one command. (Unless you change a complete configuration of course)