Some info from myselfI learned about the 65816 in 1985 when I was working for Elektuur, a Dutch electronics magazine, also known as Elektor in some other countries. They developed a processor card for some of their build-your-self computers and it could be equipped with either the 6502, 65802 or 65816. Here I could lay my hands on a 65816. I rebuild the card in such a way that it could be used to replace the 6502 on any board. Unfortunately the 65816 got damaged and that was the end of those experiments.
In 1997 I could obtain some other 65816s and started the experiments again. I succeeded in letting my PETs and CBMs run on the 65816 but failed with the VIC-20. In January 1999 I build the 6502 -> 65816 module. To my big surprise this module worked fine with the VIC-20 as well. Only then I found out that the "small-board-version" of the VIC-20 uses the CLK1 signal that my Elektor card could not supply. I didn't know of this CLK1 line as I only had schematics of the "big-board-version" which does not use CLK1.
Western Design still makes the 65SC816 and they also provide datasheets: 65SC816
The 65802 is the 6502-pin compatible version of the 65816. The main difference: it lacks the feature of addressing 16 MB.
Remark: it seems to be be extremely rare.
Using the complete 16 MB rangeThis info is only interesting if you have plans replacing a 6502 or its equivalent with the 65816.
The 65816 is capable of addressing 16 MB. To be able to do this, we need eight additional address lines. The 65816 does not provide them as seperate line but by multiplexing them with the data lines. The simplest way to generate the address lines out of the data bus is connecting a 74ALS573 8-bit latch to it and clocking it with the inverted CLK0.
Unfortunately the original system has no means to deal with these eight extra address lines ie. they are not decoded in any way. This simply means that the original system is mirrored over all the segments. Decoding these extra address lines is not the problem. Being able to handle the original system as part of the whole is.
The trick I use is to fool the original system. I placed buffers between 65816 and the data bus, address lines and R/W-line. The moment the 65816 selects any other segment then the first one, these buffers are tri-stated. Pull-up resistors will pull all lines high. For the original system it will appear as if the 65816 wants to read $FFFF. And the resistors won't jeopardize any other activity like updating the video screen in the way the C64 does.
A 74LS682, an 8-bit comparator, and an inverter can be used to determine when the first segment is selected. The output of the 682 is fed, through the inverter, to the 'Output Enable' of the various buffer ICs.
Using the RDY inputAfter building my VIC-20 PC, I found out that, using the above circuit for latching the 573, I ran into problems. When negating RDY, the 65SC816 stopped outputting the Address lines 16..23 to the data bus when CLK0 = (L). On its turn this meant that the momentary data was clocked into the latch and not the address. And this made the VIC-20 crash.
This means that we have to halt the latching the moment RDY is active. And even here we can run into problems because the decision of the 65SC816 whether to react or not to react on the RDY input depends on the point when RDY was activated. So I decided to take things in my own hand.
The 65SC816 can also be halted by keeping CLK0 (H) as long as you want. Controlling CLK0 means controlling the 65SC816 but also controlling the latch.
The idea is simple: the moment CLK=(H) and RDY=(L), CLK0 will be kept (H) until both CLK and RDY are (H) again.
CLK0 follows CLK as long as input 5 of NAND gate IC2B remains (H). NAND gates IC1A and IC1B together make a Flip-flop. The moment CLK=(H) and RDY=(L), input 1 of IC1A becomes (L), causing output 6 of IC1B becoming (L) as well and causing on its turn CLK0 to remain (H), independent from CLK.
The moment both CLK and RDY are (H) again, the Flip-flop is reset and CLK0 will follow CLK again.
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