In generalThe 6530 is a general purpose IC, it contains up to 15 bits of I/O, 1 KB of ROM and 64 bytes of RAM. Not only the ROM but even the way the whole is organised is mask programmable.
The pin outs
+---------------------+ GND -+ 1 40 +- PA1 | | PA0 -+ 2 39 +- PA2 | | CLK2 -+ 3 38 +- PA3 ___ | | RS0 -+ 4 37 +- PA4 | | A9 -+ 5 36 +- PA5 | | A8 -+ 6 35 +- PA6 | | A7 -+ 7 34 +- PA7 _ | | R/W -+ 8 33 +- DB0 | | A6 -+ 9 32 +- DB1 | | A5 -+ 10 31 +- DB2 | 6530 | A4 -+ 11 30 +- DB3 | | A3 -+ 12 29 +- DB4 | | A2 -+ 13 28 +- DB5 | | A1 -+ 14 27 +- DB6 | | A0 -+ 15 26 +- DB7 ___ | | RES -+ 16 25 +- PB0 ___ | | IRQ/PB7 -+ 17 24 +- PB1 | | CS1/PB6 -+ 18 23 +- PB2 | | CS2/PB5 -+ 19 22 +- PB3 | | +5V -+ 20 21 +- PB4 +---------------------+ PA0..PA7 = Port A, 8 programmable I/O lines PB0..PB7 = Port B, 8 programmable I/O lines DB0..DB7 = data bus A0..A9 = address bus CLK2 = Clock of the processor, also known as PHI2 RS0 = CS line, used to choose between ROM and RAM / I/O R/W = Read/Write line RES = Reset line IRQ = Open Collector output, to be connected with IRQ input of CPU CS1, CS2 = two other CS linesThe pin out-diagram shows the general overview of the 6530. Two of the 16 I/O lines, PB5 and PB6, can be used as a chip select line. "Whether these pins are used as chip-selects or peripheral I/O pins is a mask option and must be specified when ordering the part" (source: "KIM-1 Hardware manual" by 'MOS TECHNOLOGY INC.'). Not only the function of those pins could be specified, it was even possible to specify where the timer, RAM and I/O lines had to appear within the memory map. In this way you can connect several 6530s parallel to each other at the data bus without the need of extra decoding logic. This feature is used in the design of the KIM-1: it has two 6530s onboard but you won't find any logic selecting the separate ICs.
As you can see PB7 has an extra functionality as well: it can serve as an I/O line as well as an IRQ output.
The registersThe 6530 has 16 registers but 4 of them, 8..B, are probably mirrors of 0..3. The first four are involved with the I/O lines. The other registers allow the user to specify a preset count of up to $FF and a clock divide rate of 1, 8, 64 or 1024 by writing to one of the involved registers. As soon as the write occurs, the timer counts down at the clock frequency divided by the divide rate. The current timer count may be read at any time. The timer may be programmed to generate an interrupt when the counter counts down past zero. At this moment the divide rate is automatically set to 1 and the counter continues to count down. This gives the user a mean to determine how many clock cycles have past since the counter reached zero.
Register: R/W: Purpose: 0 X Data Register A 1 X Data Direction Register A 2 X Data Register B 3 X Data Direction Register B 4 0 Count down from value, divide by 1, disable IRQ 1 ??? 5 0 Count down from value, divide by 8, disable IRQ 1 ??? 6 0 Count down from value, divide by 64, disable IRQ 1 Read current counter value, disable IRQ 7 0 Count down from value, divide by 1024, disable IRQ 1 Read counter status, bit7 = 1 means counter past zero 8 X Data Register A (mirror ?) 9 X Data Direction Register A (mirror ?) A X Data Register B (mirror ?) B X Data Direction Register B (mirror ?) C 0 Count down from value, divide by 1, enable IRQ 1 ??? D 0 Count down from value, divide by 8, enable IRQ 1 ??? E 0 Count down from value, divide by 64, enable IRQ 1 Read current counter value, enable IRQ F 0 Count down from value, divide by 1024, enable IRQ 1 Read counter status, bit7 = 1 means counter past zeroThe Data Direction Registers control whether each line of the related port is an in- or output line. The Data Registers control which data is to be written to the output lines of a port or, when read, reflect the status of the input and output lines.
UseThe 6530 is used in various devices but the two most well known are:
- various IEEE dual floppy drives like the CBM 4040, 8050 and 8250
The KIM-1 has two onboard and these cannot be swapped. It is not only because the ROMs have a different content, the internal I/O mapping is different.
The 6530s of the drives are all the same except the contents of the ROM. In case of the CBM 8250-LP the ROM is disabled and an EPROM is added to the circuit to replace it. The advantage is that in case of a broken 6530, the 6530 of any other drive can be used to replace it.
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