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6522




What is it?

The 6522 is an IC of the 65xx-family supplying a system with 20 I/O-lines, two timers, a serial-to-parallel/parallel-to-serial shift register and input latching on the peripheral ports. The 6522 is also called VIA: "Versatile Interface Adapter".


Description

Control of peripherals is primarily through two 8-bit bi-directional ports. Each of these ports can be programmed to act as an input or and output. Peripheral I/O lines can be selectively controlled by the Interval Timers to generate programmable frequency square waves and/or to count externally generated pulses. Control of these functions is gained through its internal registers: Interrupt Flag Register, Interrupt Enable Register, and two Function Control Registers.


Control lines

These lines, CA1, CA2, CB1 and CB2 can act as interrupt inputs or handshake outputs. They can perform a number of different functions determined by the Peripheral Control Register (PCR). CA2 and CB2 can act as inputs or outputs in a number or modes discussed later, whereas CA1 and CB1 can only act as inputs.


The internal registers

A 6522 has 16 internal registers:
Register        Designation             Function
--------        -----------             --------------------------------------
  0             ORA or IRB              Output or input register B
  1             ORA or IRA              Output or input register A
  2             DDRB                    Data direction register B
  3             DDRA                    Data direction register A
  4             T1C-L                   T1 low-byte latch or T1 low-byte
                                        counter
  5             T1C-H                   T1 high-byte counter
  6             T1L-L                   T1 low-byte latch
  7             T1L-H                   T1 high-byte latch
  8             T2C-L                   T2 low-byte latch or T2 low-byte
                                        counter
  9             T2C-H                   T2 high-byte counter
 10             SR                      Shift Register
 11             ACR                     Auxiliary Control Register
 12             PCR                     Peripheral Control Register
 13             IFR                     Interrupt Flag Register
 14             IER                     Interrupt Enable Register
 15             ORA or IRA              Identical to register 1 but no handshake
Out/input Registers
Whether a pin is an in- or output depends the Data Direction Register. The data from as input defined pins is latched in the so-called Input Registers (IRA, IRB) at the moment of an active transaction of CA1 or CB1. Whether these Input Registers are read or the actual data is uotputted at the pins, depends on bit 0/1 of ACR.


Data Direction Registers
These registers determine the direction of each pin of port A or B and are interpreted as follows:
A '1' defines the corresponding pin as an output. A '0' defines the corresponding pin as an input.


Pin outs

          +---------------------+
   GND   -+  1               40 +-   CA1 
          |                     |
   PA0   -+  2               39 +-   CA2
          |                     |    
   PA1   -+  3               38 +-   RS0 
          |                     |    
   PA2   -+  4               37 +-   RS1 
          |                     |
   PA3   -+  5               36 +-   RS2
          |                     |
   PA4   -+  6               35 +-   RS3
          |                     |    ___
   PA5   -+  7               34 +-   RES
          |                     |
   PA6   -+  8               33 +-   D0
          |                     |
   PA7   -+  9               32 +-   D1
          |                     |
   PB0   -+ 10               31 +-   D2
          |        6522         |
   PB1   -+ 11               30 +-   D3
          |                     |
   PB2   -+ 12               29 +-   D4
          |                     |
   PB3   -+ 13               28 +-   D5
          |                     |
   PB4   -+ 14               27 +-   D6
          |                     |
   PB5   -+ 15               26 +-   D7
          |                     |
   PB6   -+ 16               25 +-   PHI2
          |                     |
   PB7   -+ 17               24 +-   CS1
          |                     |    ___
   CB1   -+ 18               23 +-   CS2
          |                     |      _
   CB2   -+ 19               22 +-   R/W
          |                     |    ___
   +5V   -+ 20               21 +-   IRQ
          +---------------------+
  
PA0..PA7  =  Port A, 8 programmable I/O-lines
PB0..PB7  =  Port B, 8 programmable I/O-lines
CA1..2
CB1..2    =  control lines
D0..D7    =  data bus
RS0..3    =  address bus
PHI2      =  Clock of the processor, also known as PHI2
R/W       =  Read/Write-line
RES       =  Reset-line
IRQ       =  Open Collector outputs, to be connected with IRQ-input of CPU CS0..2    =  Three CS-lines




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