6520
What is it?
The 6520 is an IC of the 65xx-family supplying a system with 20 I/O-lines. The data books self don't mention it, but it is said that it is completely compatible with the 6821 of Motorola. I tested this with replacing a 6520 of a CBM 8032 and things worked without any problem.
Description
The 6520 has two 8-bit I/O ports, A and B, which are mostly identical in function. All 8 bits can be set to input or output independently. Each port has 2 control lines: CA1, CA2, CB1, CB2. CA1 and CB1 are input only, CA2 and CB2 can be input or output.The 6520 has two interrupt lines: IRQA and IRQB. They may go low on a change on the inputs of the control-lines. These interrupts may be enabled on either a negative or positive transition. The selected transition is called the "active transition". Reading the appropriate PORT register resets the flags, which register that an active transition has occurred.
Registers
The 6520 has four registers:- 0 PORT A or DDR A (Data Direction Register A)
- 1 CRA: Control Register A
- 2 PORT B or DDR B (Data Direction Register B)
- 3 CRB: Control Register B
Control register
For CRA the register looks like:
bit meaning
--- -------
7 CA1 active transition flag. 1= 0->1, 0= 1->0
6 CA2 active transition flag. 1= 0->1, 0= 1->0
5 CA2 direction 1 = out | 0 = in
------------+------------+---------------------
4 CA2 control Handshake=0 | Manual=1 | Active: High=1 Low=0
3 CA2 control On Read=0 | CA2 High=1 | IRQ on=1, IRQ off=0
Pulse=1 | CA2 Low=0 |
2 Port A control: DDRA = 0, IORA = 1
1 CA1 control: Active High = 1, Low = 0
0 CA1 control: IRQ on=1, off = 0
CRB works identical for CB1 and CB2, except for the differences in handshaking. The Cx2 handshake is not identical between ports. For port A, the handshake is on reading PORT A, for CB2 the handshake is sent on writing to PORT B.
The handshake mechanism
We assume that both CA1 and CB1 have an active transition from (H) -> (L). The moment a byte is written to Port B, CB2 is set (L) ("Data is sent"). Normally CB2 is connected with CA1 so this line becomes (L) as well. This active transition causes CA2 to become (H) signaling the processor "Data valid". Reading Port A sets it (L) again ("Data accepted"). As CA2 is connected with CB1 normally, this line becomes (L) as well. This active transition causes CB2 to become (H) signaling "Ready for transmitting new data".Setting bit 3 to (H) causes CA2/CB2 to output one low pulse for one cycle only after a read or write operation. This pulse may be too short for some uses and is therefore not often used.
Pin outs
+---------------------+
GND -+ 1 40 +- CA1
| |
PA0 -+ 2 39 +- CA2
| | ____
PA1 -+ 3 38 +- IRQA
| | ____
PA2 -+ 4 37 +- IRQB
| |
PA3 -+ 5 36 +- RS0
| |
PA4 -+ 6 35 +- RS1
| | ___
PA5 -+ 7 34 +- RES
| |
PA6 -+ 8 33 +- D0
| |
PA7 -+ 9 32 +- D1
| |
PB0 -+ 10 31 +- D2
| 6520 |
PB1 -+ 11 30 +- D3
| |
PB2 -+ 12 29 +- D4
| |
PB3 -+ 13 28 +- D5
| |
PB4 -+ 14 27 +- D6
| |
PB5 -+ 15 26 +- D7
| |
PB6 -+ 16 25 +- PHI2
| |
PB7 -+ 17 24 +- CS1
| | ___
CB1 -+ 18 23 +- CS2
| |
CB2 -+ 19 22 +- CS0
| | _
+5V -+ 20 21 +- R/W
+---------------------+
PA0..PA7 = Port A, 8 programmable I/O-lines
PB0..PB7 = Port B, 8 programmable I/O-lines
CA1..2
CB1..2 = control lines
D0..D7 = data bus
RS0..1 = address bus
PHI2 = Clock of the processor, also known as PHI2
R/W = Read/Write-line
RES = Reset-line
IRQA/B = Open Collector outputs, to be connected with IRQ-input of CPU
CS0..2 = Three CS-lines
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