1541: Transferring data
BackgroundI found a lot of documents about the 1541 but 99% of the information was about how to program this device. This information went as "deep" as programming both the 6522's. But almost nothing was found about how the data is written to or read from the floppy disk self. This makes some sense as the user has no control of this part of the 1541. So I decided to make some documentation about this part of the 1541 my self.
The hardware for transferring data from/to the floppyThe 1541 came in several versions. Except from the very first version all boards are equipped with one or more custom ICs, like the 325572-01. And as there is no info available about these ICs (AFAIK), I had no idea what was going on inside these ICs.
But it is a fact that the brown 1541 with this custom IC is 100% compatible with its white ancestor. This white 1541 contained a longer board only equipped with known TTL ICs. So my conclusion was that this custom IC replaced these TTL ICs not found on the board of the brown 1541. So I made a schematic of this part using the original paper schematic of a 1540 as base. I used the IC codes used in this paper schematic to name the ICs in the new one.
The main clock circuitSomewhere on the main board a 16 MHz signal is generated. A 74177 divides this frequency by 16 to clock the 6502. The 16 MHz signal is also used to clock a 74LS193, a pre-loadable up/down counter (UE7/1540, UE6/1541). In this case the 193 only can count up. The pre-load inputs A and B are connected to PB5 and PB6 of one of the 6522's. These are the 'density bits'. Depending to the values of PB5 and PB6, the 193 can count up starting from 0, 1, 2 or 3. Normally for tracks 1-17 the clock divisor is 13, for tracks 18-24 it is 14, for tracks 25-30 it is 15 and for tracks 31-35 it is 16. The reason for this is that the outside of a disk moves faster. The faster a track moves under a head, the faster the bits can be read or written. The smaller the divisor, the faster the read/write operation can be performed.
The moment the 193 counts from 16 to 17, a Carry is generated at pin 12. This signal is used to pre-load the 193 again. Two NOR gates (UE5c and UE5d, 74LS02), are used to combine the Carry with the output of a 9602. About this IC later.
The inverted Carry pulse is further used to clock UF4, another 193, which is used as a straight-on binary counter. Its output QB is used to clock most of the other parts. This means that by manipulating PB5 and PB6 you determine the speed by which all actions take place.
Writing data to the floppy diskBy negating output CB2 of 6522#2, the writing process is started. This signal performs three things:
- The 9602 is disabled. This means that no positive pulse is generated so UE7, the first 193, is only reset by its own Carry signal.
- The 245, UC3, used as last stage in reading data from the floppy, is disabled using the inverted signal (inverted by UF5a, a 00).
- The above inverted signal, now (H), is fed into another gate of UF5, UF5d. This gate enables the hardware to write to a floppy.
The data outputted by port A of 6522#2 is read by UD3, a 74LS165 parallel-to-serial shift register. The data is loaded at the moment that UE3, a 191 binary counter, has counted 8 pulses from UF4's QB output. Its outputs QA, QB and QC are ANDed using a 74LS10 3 input NAND gate (UF3a) and an 74LS14 inverter (UC1c). This signal is NANDed with UF4's QA and QB output. The result is used to clock UD3.
The signal coming from the UC1c is also NANDed with the inverted QB of UF4 and the SOE signal coming from 6522#2. The result is fed to the CA1 input of 6522#2 and to the SO input of the 6502. This signal is the so called "Byte ready" signal. As the name already explains, this signal actually tells the processor that eight bits (= byte) have been written to the disk. But be aware, when writing data to port A of 6522#2, the first active "Byte ready" signal means the data is clocked into the 165 and only the second signal means the data is actually written to the disk!
The bits loaded by UD3 are outputted at its QH output using the already mentioned UF4's QB output as clock.
The output is NANDed with this clock signal as well and fed into the clock input of UF4b, a 74 D-flipflop. Its /Q output is connected to its own Data input. In this way both outputs toggle every time QB makes a transition from (L) to (H) AND the bit to be stored is a 1. The conclusion is that a 1 is stored on a disk as a change of the magnetic field. When the bit is a 0, the field does not change.
As said before, UF5d enables the hardware to write to the floppy. Its first input comes is connected to 6522#2 through another 00. Its second input is steered by the optocoupler used to detect if the floppy is write-protected or not. The moment the floppy is read or write-protected, the output of UF5d becomes (H). This signal is inverted again by UF5c. Its output is connected to the Preset and Clear input of the UF4d flipflop. A (L) at both these inputs sets both outputs to (H). The output of UF5d is inverted again through UG2c, an 86 EXOR, to disable at the end Q3, a NPN transistor. This transistor sinks the current coming from the coils of the head. If the transistor is disabled, no current can flow through the coils ie. no data can be written.
Reading data from the floppy diskAs already said, a 1 is stored on the floppy disk as a change of the magnetic field. These changes cause pulses in the coils when the floppy is read, which are processed by several OPAMPs and a digital circuit. In the 1540 one part of this digital circuit is the 9602.
First I had no idea how this IC worked. Then I was told there were two versions of the 1541-board. So I looked in my archive and hardware storage and found another, different schematic of the 1541 as well as the mentioned board.
The most interesting difference was that this board used a 74LS123 instead of an 9602. The 123 is a retriggerable monostable multivibrator. The Q output outputs a positive pulse which duration is determined by a RC-combination. The pulse can be shortened by negating the CLR input or extended by retriggering the 123 before the time of duration of the pulse. As I found no further difference in the circuit handling the read pulses, my conclusion was that the 123 was a non-pin compatible replacement for the 9602. For further explanations I made a schematic . The showed mix of a 74LS123 and a 74LS74 does NOT exist in reality. To avoid further confusion I will use the IC codes generated by my schematic editor.
To be honest, I only have a vague idea how the pulse produced by the coils is processed by the analogue part, but my conclusion is that the 311-OPAMP, U4, outputs a pulse long enough to be read by the U2a, the 74LS74. The 74 inputs the data at a positive transition of the clock. This positive transition will occur after the U3B, the 74LS123, has been triggered by U1a, a 74LS86, and a certain time, defined by R3 and C2, has passed. My personal conclusion is that the length of a pulse depends on the strength of signal generated by the coils.
The function of U1a, an EXOR gate, is to produce a pulse whenever the 311 produces a positive or negative edge. This pulse triggers the 123.
Remark: The CLR input is connected to CB2 of 6522#2. And CB2 determines whether data is written to or read from the floppy. We already knew that when CB2 is (L), data is written to the floppy. This means that the first 123 continuously is cleared ie. it won't produce any pulse at all. The reason for this is that the signal sent to the coils is picked up by the OPAMPs as well. A 1 would cause a reset of UE7 and this could, because of the delay times, mess up the whole procedure.
The output of the 74 is used to generate another pulse using another EXOR gate and the second half of the 123. This pulse, coming from pin 13, is the one going to U5d and UF4 at the spot marked as 9602 in the 1540-schematic .
Now IMHO something happens what I do not completely understand. At the end of the pulse coming from the 311, the 123 is triggered again. This causes the Q output of the 74 to change level. This change of level triggers the second half of the 123 to produce another pulse at pin 13 again. Now two possible situations can occur:
- The pulse at pin 13, started by the first transition of the 74's Q output, is still going on. In this case it is extended by another time period.
- The 123 was in rest so another pulse is outputted. Again two situations can occur:
- The second pulse is within 125 ns. UF4 is cleared before its QB output could produce a clock pulse. Without this pulse UD2, the 74LS164 serial-to-parallel register, only clocks one 1.
- The second pulse appears after more then 125 ns. Two 1's are clocked. If this really is the case, then my theory about the 311 outputting a pulse for every 1 is completely wrong :( This would mean that the output of the 311 changes level whenever a 1 is read. But a coil only picks up changes in a magnetic field and, IMHO, the analogue part does not contain a flipflop function.
Input Output -------- ------ QB QC QD L L L H H L L H L L H L H L H L L H L L H H L L L H H L H H H L
Nibble 0000 -> 01010 0001 -> 01011 0010 -> 10010 0011 -> 10011 0100 -> 01110 0101 -> 01111 0110 -> 10110 0111 -> 10111 1000 -> 01001 1001 -> 11001 1010 -> 11010 1011 -> 11011 1100 -> 01101 1101 -> 11101 1110 -> 11110 1111 -> 10101
The data is clocked into the 164 on a positive transaction of QB. We already know that it takes two Carries from UE7 to cause QB to become (H) after a reset. So after reading the first three bits, 100, the second 1 must show up before the second Carry after clocking in the second 0. IMHO this would mean speed of a drive could drop as low as 225 RPM before an error will occur.
A 1, that shows up shortly after the second 0 has been clocked in, will be noted as well. This would mean that a drive can be too fast for up to 375 RPM.
Personally I have the feeling that the above theory is wrong but I cannot say you why.
Remarks: A drive that is too fast will have trouble formatting a track. Drives that are too fast or too slow, but within the mentioned 25%, will also have troubles when writing to a disk. Or better, trouble with reading the data after it has been written. But for the moment I skip any explanation of these remarks.
UE3, the 74LS191 binary counter, here also checks if eight bits have passed the head. If this is the case, a "Byte ready" signal is generated by UF3c. As said, this signal is fed to the CA1 input of 6522#2. 6522#2 is programmed so that, when reading port A, the data is read which was latched during the positive-to-negative transition of CA1. The reason for this latching is that the data on the outputs of UD2, the 74LS164 shift register, is only valid for 3 cycles.
UC3, the 74LS245 bidirectional buffer, outputs the bits, which are clocked in by UD2. The moment synchronization bytes (= $FF) are encountered, all outputs of the 164 become (H). The sync bytes are used to mark the beginning of blocks containing data or information. The outputs of the 164 and three other signals are NANDed (UC2, 74LS133) to produce the so called SYNC signal. This signal is used to tell the processor that the head is above an area with these sync bytes. It is also used to reset the binary counter UE3.
One of the three signals mentioned above, is the MODE signal. This simply means that the SYNC signal only can occur during read sessions.
The two other signals are produced by the two halves of UE4, a 74LS74 D-flipflop. The first FF reads QH of the 164 and outputs its Q output to the data input of the second half and to UC2, the NAND gate. The output of the second half also goes to UC2. This simply means that we must have at least ten 1s in row for the drives signals the processor that it has found a sync byte.
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