6510 -> 65816
What is it?
This projects tells you how you to replace your 6510 or 8502 with a small board containing a 65816, 6526, some buffers and some glue logic. Except desoldering your 6510/8502 (if needed at all), no other soldering on the original board is needed.Remark: from now on I will only mention the 6510 when meaning BOTH the CPU's.
The (dis)advantages of replacing your 6510
I received emails like: "I replaced my 6510 but my system didn't become faster" and "How can I address 16 MB?" So before you start to grep your soldering iron, ask yourself: "Do I need this modification?"First remark: Replacing a 1 MHz 6510 with a 4 MHz 65816 does not mean that the system suddenly becomes four times faster: a 65816 is as fast as the clock it is fed with!
I have studied the specs of the 65816 to see if it did optimize some opcodes. But IMHO it didn't so it is as fast as a 6502. So no gain here either.
Second remark: The 65816 has more opcodes. And the new ones replace some so called "illegal" opcodes. So if you run programs using these illegal opcodes, you certainly will run into trouble sooner or later.
Third remark: The 65816 is capable of addressing 16 MB. But it needs extra hardware to be able to do this trick! And as the C64 and C128 simply don't provide this hardware, no 16 MB!.
FYI: I replaced the 6502 of a VIC-20 with a 65816 and added some extra logic so now it is able to handle PC ISA-cards!
The story
In 1985 I could lay my hands on a 65816 processor. During my first experiments to replace the 6502 of a VIC-20 with this uP it broke down :( In 1997 I could lay my hands on several 65816's for peanuts. So after 12 years I could resume my experiments. This resulted in a small module which you simply put in the place of the original 6502: 6502 -> 65816.It was obvious to perform the same trick for the 6510. I built a quick-and-dirty hack that worked fine as long as the original onboard I/O port wasn't needed. So that meant finding a replacement for the onboard I/O-port.
The differences between the 6510 and 65816
The 65816 lacks the CLK2 clocksignal so we have to provide it ourselves. That's where two 74F04-inverters come in view, U1a and U1b. U1a generates PHI1, U1b generates PHI2.ABORT is a 65816-specific input and can be tied to +5V. You can add a resistor if you think you can use this input in the future.
Using a 6526 will solve the missing I/O-port.
The schematics
6510-version
8502-version
How does it work?
Replacing the 6510 is quite forward and doesn't need an explanation IMHO. The I/O-port is a different matter. First we need some replacement for the port it self. The most simple solution is to take a 6526 (U7) from an obsolete C64. We only need register A. To address it as the 6510 addresses its own onboard port, we have to place an inverter (U1c) between addressline A0 and input RS1. The other RSx-inputs are tied to GND.The next step is selecting the IC. A 682 (U3) and 688 (U2) comparator perform this function. Accessing the onboard port is an INTERNAL matter for the 6510. In our case the 6526 is an EXTERNAL port. This means that when the 65816 outputs the address $0000 or $0001, we have to provide some means to avoid the RAM to interfere with the actions of the 6526. These means are a 245-bi-directional buffer (U6) plus some glue-logic.
The databus of the 6526 is connected directly to the databus of the 65816. All other data traffic has to travel through the 245-buffer (U6). The buffer has to be tri-stated when:
* the 65816 has to access the 6526
* the VIC wants to tristate the CPU
This is realised by NANDing (U8a) the output of the 688 with the AEC-signal coming from the VIC. The output of the NAND is fed to the enable-input of the 245.
The 8502
The differences with the 6510 version are minor: the 8502 has an extra I/O-pin and lacks the PHI2-pin.A little simplification
As you can see I used only 1 NAND gate and three inverters. One could save an IC by replacing the three inverters by the three NAND-gates. But a remark: during my first experiments in 1985 I encountered some problems regarding the timing of the generated PHI2. From that day on I only used 74F04 inverters. So if the simplification doesn't work out, you know why.A small addition
To test this board I needed some means to be able to halt the 65816. So I used two NAND-gates to create an AND-gate which I placed between the RDY-input of the 65816 and the signal coming from the board.Using the complete 16 MB range
Remark: the next part is just an idea and hasn't been realised yet !!!Please see: 65SC816 in the first place. Here you can read that need an extra 573 or equivalent to generate the address lines A16 to A23.
The extra segments can be used for extra memory and I/O. I once expanded the memory of a C64 by replacing the original 4164s with the 41256. The extra memory could be accessed through banking.
Installing 41256's also means we need an extra 74LS256 for handling the extra multiplexed address line of this IC. No problem so far IMHO; A16 and A17 are connected to the two inputs, the corresponding output goes A8 of the 41256's.
The next problem is the PLA and the VIC. In a normal setup reading the address $E000 means reading the Kernal ROM. But reading $01E000 should mean reading from the extra RAM but how are we going to tell this the PLA? IMHO negating the A15 input will do the trick. This makes the PLA think that the C64 is accessing the address range from $0000 to $7FFF and no special handling like accessing I/O or (external) ROM is needed. ANDing this signal with the 'not first segment' signal can do the trick.
The VIC must be able to access the memory in the first segment, independent of what the values of the address lines A16..23 are. For this reason I choose the 256. The 256 does not tristate its outputs like the 257 does, but pulls all outputs to (L), resulting in an automatic selection of the first bank.
Remark: remember that when no extra decoding is done, the resulting 256 KB range is mirrored all over the rest of the 16 MB. So for extra RAM or I/O on top of this expansion, extra decoding is a must.
Adding even more RAM can be realised by piggybacking it on top of the already installed 41256's. (How much layers can the power supply and drivers endure ???) Then it is a matter of diverting the CAS-signal to the right layer using a de-multiplexer like a 74LS139.
Another thought is using 30-pins SIMs providing 1 MB, 4 MB or even more. Unfortunaly these memory modules need another refresh scheme than the 4164 and I haven't found a way yet to adapt it to the needs of these modules :(
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