Ruud's Commodore Site: 6510 -> 65816 Home Email

6510 -> 65816




What is it?

These are various ideas how to equip you C64 with the famous 65816 processor. The ideas range from very basic up to one idea with even an ISA slot that enbales you to use 8-bit PC cards.


The (dis)advantages of replacing your 6510

Just be aware of the fact that the 65816 doesn't support any of the 6510's so called "illegal opcodes". Programs using these opcodes will malfunction and most probably crash!
One advantage is that you gain new commands and the CPU won't hang on some codes. Depending on the type of expansion, you gain a lot of goodies like extra RAM, ROM and I/O.


Version 1


Version 1 is the most basic one: it just replaces the 6510 with a 65816, 6526 and some glue logic. The idea is simple:
- the 65816 replaces the 6510
- the 6526 provides us with I/O pins so we can emulate the onboard port of the 6510
- a bi-directional buffer
- some logical circuits

Why the buffer? The 6510 addresses its ports at the addresses $0000 and $0001 and this is an internal affair. To keep it internal, we have to separate the 6526 from the rest of the system and that is where the bi-directional buffer, a 74LS245, steps in.
The 6510 can be tristated so this 245 buffer must be tristated as well. Unfortunately the level of the signal to tristate the 6510 is a (L). No problem for the 65816 but the 245 will be tristated with a (H). So we need an inverter to correct this.
The 245 buffer also has to be disabkled the moment the 6526 is addressed. This would mean a second inverter but we combine the one mentioned above with this one in the form of an AND gate, IC4A.
And what about these "logical circuits"? As said before, the 6510 talks to its ports over the addresses $0000 and $0001. So we need means to create this small range. Two 688 8-bit comparators will do the trick. The 6526 then mimics the behavior of the original port more or less right out the box. First we have to connect address line A0 to input A1 but only after it has been inverted.
The 65816 does not generate PHI2 so we have to create it out of PHI0 ourself. This is done by using two 74F04 inverters. I simply have no idea yet if LS or other types will work as well but from pure experience I know that these will do fine.

When working on the GAL version the idea rose to use the rest of the 6526 as well in one or another way. So I connected the other needed address lines to the 6526 and added another 688 comperator to select the $D7xx range. Why $D7xx? This is the only range that is free in the C128. If this idea works, why not creating a cord for the C128?


Version 1 with GAL


The only difference with the original version is that the three 688 comparators have been replaced by one GAL. The main advantage: it saves space, thus a smaller PCB. I had hoped that the GAL also could provide a delay between PHI0 and PHI2. Unfortunately the equation for creating the CS signal for the 6526 became too large and had to be split in two. No free pins left meant I had to discard of a function and, not being sure if the delay trick with the GAL would work, I dropped it.


The PCB





The equations for the GAL

To be done yet


Version 2, expanding version 1


This idea is an expansion of the circuit above. I freed memory in the ranges meant for the VIC and SID and reserved 512 bytes for the extra ROM, 512 bytes for the extra RAM and 256 bytes for the extra I/O of the 6526.
The extra eight bits of port B are used to page the extra RAM and ROM; just 512 bytes of each would make no sense IMHO. Eight bits is good enough to end up with 128 KB of each.
Probably the big question: why the two 74LS541 buffers in the address lines and the 74LS125 buffer between the 65816 and motherboard? The moment you address the extra RAM, ROM or I/O, you also will address the VIC or SID. That is, if you don't take actions. My solution: disable the address lines and R/W line at that moment and pull them (H). The board will read from $FFFF and AFAIK nothing will happen.
As said, this was just an idea and I won't work this one out into a PCB and GAL equations for a simple reason: I want to make an even better use of the 65816.


Version 3


This version makes use of the 65816's capabilities to address more than the 64 KB of memory or I/O that the 6501 or 6502 can address. In this case I will only go up to 1 MB instead of the maximum of 16 MB. Reason: one big ROM and one big RAM IC of 512 KB each is enough. But in fact I want even more, see version 4. So no PCB for this version as well.

To be able to address this 1 MB, we have to create the address lines A16..19 first. The 65816 multiplexes these lines with the data lines: when PHI0 is (L), the data bus outputs the address lines A16..23 and when PHI0 is (H), it outputs or reads the data. The address lines are latched using a 74ALS573, IC9, that is clocked by PHI1 (see later).
The 65816 will start up in 6502 mode which means that all actions will take place in Bank 0 for the moment. This simply means that the C64 has to reside here. But how does the C64 knows it resides in Bank 0? Simply, it doesn't and how should it? But every time the 65816 has business to do with any other bank than Bank 0, we will use the same trick as the one mentioned in version 2: buffers make the C64 think the CPU is reading address $FFFF. A third 688 comparator, IC4, checks whether Bank 0 is selected i.e. address lines A16..19 are (L), or not. The line that signals this to the rest of the circuit is called ORG.
OR gate IC12C combines this signal with the NANDed combination of AEC signal and the enable signal for the 6526 (IC10A): the buffers are only active now if Bank 0 is chosen and AEC is active (H) and the 6526 is not selected.

I want to connect a 512 KB SRAM and a 512 KB FlashRAM. I will loose 64 KB of one of them because I need Bank 0 for the C64. I still haven't made a decision yet: a bit more of RAM or a bit more of ROM? But I'm not going to build this design anyway so in fact it doesn't matter.
How to select this RAM and ROM at all? A 138 takes care of that. It does this by using the Bank 0 signal as first input to make sure that either ROM or RAM is meant and address line A19 selects whether it is RAM or ROM. PHI1 makes sure that the timing is correct.

What I really miss in the C64 is a way to halt it. I cannot use the DMA pin at the expansion port because negating this pin not only halts the 6510, but also tristates it. So I added jumper JP2 which gives us a mean to feed an external RDY signal.
So now I have two sources for the RDY signal:
- the signal coming from the motherboard
- the external signal coming from jumper JP2
The first one placed me for a dilemma: if the 65816 is running a program in any other bank than Bank 0, should it react to a signal coming from the motherboard? If the originator is the VIC, just wanting some extra time to access the video memory, we can ignore it. If the originator is the REU for example, I personally think we still can ignore it. But I feel a bit uneasy about it. Anyway, OR gate IC12A makes sure the RDY signal coming from the Motherboard is ignored when the 65816 accesses any other bank than Bank 0. AND gate IC22A mixes the resulting signal and the one coming from jumper JP2.
The block of logic gates, roughly bottom/middle of the schematic, has only one function, handling the final RDY signal coming from the AND gate. Why there are such a lot of gates will be discussed on this page.

Version 4


But I wasn't satisfied yet. Extra RAM, extra ROM, but no extra I/O. To make a long story short, I added the 8-bit PC ISA bus as found in the original IBM PC/XT and its clones. My original idea was to incorporate the 512 KB of RAM and only 128 KB of ROM of version 3 into the memory range of the ISA bus, being 1 MB, reserving 64 KB for I/O and the rest for whatever card was stuck into the slot. But hey, why not being generous? By adding two address lines I could use 1 MB for RAM, 1 MB for ROM, 1 MB for the memory part of the ISA bus and 1 MB for the I/O of the ISA bus. OK, in case of the I/O the complete range is only 1024 bytes but that won't disturb the fun.
But to stay realistic, I will only use 512 KB of RAM and ROM. In the IC version they will mirrored inside their 1 MB range but in the GAL version I will tinker with the equations so they occupy only 512 KB.

In the original verion I also replaced the origal Kernal ROM with a 512 KB flashRAM and in such a way that this PCB would replace the 6510 and the Kernal ROM. I was also working on a VIC-20 version when the idea hit me that extra ROM could also replace the Kernal and BASIC ROM just by connecting some extra address lines to the GAL of the 6502 version. Better, for that I even didn't have to remove the original ROMs! It was more or less logical to use the idea here as well.

The hardware on the left side of the schematic is, with the exception of IC22A, the same as the one of version 3 and therefore needs no further explanation IMHO. The difference starts with IC3, the 573 that generates the address lines above A16. Instead of four, six lines are generated: A16..21. These are good for a memory range of 4 MB. IC13, a 138 demultiplexer, splits it up in four parts of 1 MB using the address lines A20 and A21. PHI1 makes sure the timing is alright. Connecting pin 6 to the output of IC4, the 688 comparator for the highest address lines, signal ORG disables the 138 the moment Bank 0, the C64, is selected.
Output Y0 selects the ROM. Being a 512 KB ROM in a 1 MB range means it will be mirrored. Range: $200000-$2FFFFF. But then there is IC24, another 138. It generates a (L) when the BASIC or Kernal ROM are selected in the very first 64 KB. These two signals are combined with the above ROM signal and the result is fed to the FlashRAM.
Output Y1 selects the RAM and it is also mirrored. Range: $300000-$3FFFFF.
Outputs Y2 and Y3 select the ISA bus. AND gate IC16B combines both signals and enables IC17A, a 139. IC17A generates the signals MEMR, MEMW, IORD and IOWR out of the 65816's R/W line and address line A20.
When selecting output Y3, the second 1 MB in the range, all memory attached to the ISA bus can be handled. Writing a byte to $1B8000, for example, will write a byte to the video memory of a CGA card.
Output Y3 selects the RAM and it is also mirrored. Range: $300000-$3FFFFF.
From $400000 on this whole block of 4 MB is mirrored again for three times.
From $400000 on this whole block of 4 MB is mirrored again for three times.

My design doesn't support DMA so all DMA related pins of the ISA bus are left unconnected.

BALE is a weird duck. I have asked around but nobody could point me to a card using that signal. If it is meant for 74373 or 74573 latches to latch the presented address, in this case +5V will do the trick as well.

AEN is only needed when DMA is used. We don't use DMA so we tie it to Ground.

RESET is the reset signal for the ISA bus. But because it is active (H), it is inverted first using IC23F.

IOCHK is the active (L) NMI signal coming from the ISA bus. Jumper JP1 gives us the choice to connect this signal to NMI or not.

IOCHKRDY is the RDY equivalent of the ISA bus. I mixed it with the other RDY related signals using 3-input AND gate IC22A. In version 3 this used to be a 2-input AND gate.

The ISA bus has six interrupt outputs, all active (H) and not an Open Collector output. Six 7406 Open Collector inverters convert it to "one" output. Jumper JP3 enables us to tie the result to the IRQ input of the 65816, or not. I am thinking about using the unused I/O pins of the 6526 to watch the individual INT pins. If I will do it, it will be done in the GAL version.


The power supply

I don't think the C64's original power supply can support the board plus ISA bus including a card, even the PS suitable for supporting the REU. I myself think about using the card on a board from which I removed the onboard 7805 and 7812, disconnect the +5 Volt coming from the transformer and use the +5 and +12 Volt from a PC power supply that also powers the ISA card. The original PS is still needed for the 9 VOLT AC for the user port and Time-Of-Day clock.


Version 4: the GAL version


In the GAL version I want to replace as much of the glue logic and comparators with GALs. Main reasons: to save space and more flexibility in the design.

Of course I started with replacing the two comparators dedicated to the 6526 but ran into a little bummer: I wasn't able to add the "Bank 0" signal (called SEGM0 in the schematic) to the GAL16V8. So I used a GAL22V10 instead.
Replacing AND gate IC10A and IC12C was easy: I needed AEC, the enable signal for the 6526 and the "Bank 0" signal as input and one output signal. Our GAL IC2 already has two of the three input signals and has four free pins.
Still left with two free pins I decided to create an inverter with them so I could invert address line A0 and feed the result to input A1 of the 6526.
The last thing I tried was finding out if I could program the GAL in such a way that the 6526 was also accessible at $D600-$D603. This is a mirror area of the SID so that should not give problems. And yes, that was possible. So I added the extra address lines needed to address the other registers of the 6526 and used port B to read the INT signals directly at the source. I also added jumper JP4 to enable to connect the IRQ output of the 6526 to the IRQ input of the 65818.

Next step is replacing the comparator for creating the Bank 0 signal: six input signals and one output signal. The circuit that generates the ISA bus signals needs two extra input signals and generates four output ones. One GAL20V8 covers it all.

Last but not least is the circuit that handles RDY. Four input signals, four output ones and two outputs as dummy so I can create a flipflop. And one input and output pin left to create an inverter for the reset signal for the ISA bus.
The only real gates left now were the two F-type inverters that make PHI2 out of PHI0. And still having free pins I decided to use them to create a kind of delay circuit. I even added a resistor and capacitor, just in case they are needed.


Using port B of the 6526

I already had figured out that it was easy to program the 22V10 GAL in such a way that the 6526 could be addressed at the original range, $0000-$0001, and at a range of 16 bytes "stolen" from either the VIC or SID range. That meant that I could use six bits of port B for reading the individual bits of the Interrupt signals of the ISA bus. But that meant I had two bits left over. An earlier design had also the original Kernel ROM incorperated into the board, that is, replaced by a bigger EPROM. The idea was to use the left over pins to select multiple Kernals but I dropped that idea. In the end I forgot about them until rewriting this page. But then the PCB already had been ordered. OK, something for the future.


Version 4: the PCB




You maybe noticed the four power connectors in the schematic while only two would be needed. That has to do with having only one ISA slot. The idea behind only having one ISA slot is that I can stick an ISA-riser board into it which simply adds more slots:


This one has four slots at only one side but I also have risers that have slots at both sides. But sticking a card in the riser could mean that the bottom one(s) could interfere with the power connector, or "better", with the connectors and cables sticking into it. So the idea rose to solder the power connector horizontal on the board. The extra connectors give extra space to solder the pins.


Version 4: the GALs

GAL IC2
GAL IC3
GAL IC4






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