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Some info from myself
I learned about the 65816 1n 1985 when I was working for Elektuur, a Dutch electronics magazine, also known as Elektor in some other countries. They developed a processorcard for some of their build-your-self computers and it could be equipped with either the 6502, 65802 or 65816. Here I could lay my hands on a 65816. I rebuild the card in such a way that it could be used to replace the 6502 on any board. Unfortunately the 65816 got damaged and that was the end of those experiments.
In 1997 I could again lay my hands on some other 65816s and started the experiments again. I succeeded in letting my PETs and CBMs run on the 65816 but failed with the VIC-20. In January 1999 I build the 65816 module. To my big surprise this module worked fine with the VIC-20 as well. Only then I found out that the "small-board-version" uses the CLK1 signal that my Elektor card could not supply. I didn't know of this CLK1 line as I only had schematics of the "big-board-version" and this board does not use this line.

Western Design still makes them and they also provide datasheets: 65SC816

The header also mentions the 65802. This processor is a 6502-pin compatible version of the 65816. Unfortunately it lacks the feature of addressing 16 MB and it is extremely rare.

Using the complete 16 MB range
This info is only interesting if you have plans replacing a 6502 or its equivalent with the 65816.
The 65816 is capable of addressing 16 MB. To be able to do this, we need eight additional address lines. The 65816 does not provide them as so by multiplexing them with the databus. The most simple way to generate the address lines out of the data bus is connecting a 74ALS573 8-bit latch to it and clocking it with the inverted CLK0.

Unfortunately the original steps has no means to deal with these eight extra address lines ie. they are not decoded in any way. This simply means that the original system is mirrored over all the segments. Decoding these extra address lines is not the problem, being able to handle the original system as "just another IC" is. In most cases a IC is selected by negating a typical "Chip Select" input. But I haven't found any system yet that could be threatened as an IC.
The trick I use is to fool the original system. I placed buffers between 65816 and the data bus, address lines and R/W-line. The moment the 65816 selects any other segmant then the first one, these buffers are tri-stated. Pull-up resistors will pull all lines high. For the original system it will appear as if the 65816 wants to read $FFFF. And the resistors won't jeopardize any other activity like updating the video screen in the way the C64 it does.

A 74LS682, an 8-bit comparator, and an invertor can be used to determine when the first segment is selected. The output of the 682 is fed, through the invertor, to the 'Output Enable' of the various buffer ICs.

Using the RDY input
Only lately I found out that, using the above circuit for latching the 573, one can run into problems. When negating RDY, the 65SC816 stops outputting the Address lines 16..23 to the data bus when CLK0 = (L). On its turn this means that the momentary data is clocked into the latch and not the address. And this can have weird consequences.
This means that we have to halt the latching the moment RDY is active. And even here we can run into problems because the decision of the 65SC816 whether to react or not to react on the RDY input depends on the point RDY was activated. So I decided to take things in my own hand.

The 65SC816 can also be halted by keeping CLK0 (H) as long as you want. Controlling CLK0 means controlling the 65SC816 but also controlling the latch.
The idea is simple: the moment CLK=(H) and RDY=(L), CLK0 remains (H) until both CLK and RDY are (H) again.
Schematics:
PNG
Eagle