Name		ISA bus with 65816, 816ISA GAL #3;
	Device		G16V8AS;
	Designer	Ruud Baltissen;
	Date		2013-04-16;
	Revision	V0.1;

	Assembly	--;
	Company 	--;
	Location	--;
	Partno 		--;

    
/* Define Logic Operators */
	/* AND = &  */
	/* OR  = #  */
	/* NOT = !  */     


/* Define Input Pins */
/* Define Input Pins */
pin  2 = IORDY;		/* IOCHRDY signal coming from ISA bus */
pin  3 = RW; 		/* R/W coming from 65816 */
pin  4 = RDY; 		/* RDY signal coming from original system */
pin  5 = CLK;		/* PHI0 clock coming from original system */

/* Define Output Pins */
pin 12 = FF1;		/* internal flipflop output #1 */
pin 13 = FF2;		/* internal flipflop output #2 */
pin 14 = PHI0;		/* new PHI0 for 65816, including WAIT states */
pin 15 = WR;		/* Intel style WRite signal */
pin 16 = RD;		/* Intel style ReaD signal */
pin 17 = C573;		/* clock signal for adres latch */
pin 18 = PHI2;		/* generated PHI2 for original system */
pin 19 = PHI1;		/* generated PHI1 for original system */

/* Boolean Equations */
FF1   = (!(RDY & IORDY) & CLK) # !FF2;
FF2   = ( (RDY & IORDY) & CLK) # !FF1;
C573  = !CLK & FF2;
PHI0  = !C573;
WR    = !PHI0 # RW;
RD    = C573 # !RW;
PHI1  = !CLK;
PHI2  = !PHI1;


/*
FF1   = !(!(!RDY & CLK) & FF2);
FF2   = !(!( RDY & CLK) & FF2);
*/