Name		ISA bus with 65816, GAL #1  (646 version);
Device		G22V10;
Designer	Ruud Baltissen;
Date		2013-04-24;
Revision	V0.1;

Assembly	--;
Company 	--;
Location	--;
Partno 		--;

    
/* Define Logic Operators */
	/* AND = &  */
	/* OR  = #  */
	/* NOT = !  */     


/* Define Input Pins */
pin  1 = GALCLK;	/* clock input */
pin  2 = RW; 		/* R/W coming from 65816 */
pin  3 = PHI0;		/* new PHI0 for 65816, including WAIT states */
pin  4 = A15; 
pin  5 = A16;
pin  6 = A17;
pin  7 = A18;
pin  8 = A19;
pin  9 = A20;
pin 10 = A21;
pin 11 = A22;
pin 13 = A23;

/* Define Output Pins */
pin 23 = ISA;		/* $010000 - $FFFFFF for all board accesses */
pin 22 = IOWR;		/* $02xxxx  I/O write access (L) */
pin 21 = IORD;		/* $02xxxx  I/O read access (L) */
pin 20 = MEMW;		/* AT = 24 bits memory write access (L) */
pin 19 = MEMR;		/* AT = 24 bits memory read access (L) */
pin 18 = SMEMW;		/* XT = 20 bits memory write access (L) */
pin 17 = SMEMR;		/* XT = 20 bits memory read access (L) */
pin 16 = EIO;		/* $01xxxx for extra I/O for org. system */
pin 15 = IO;		/* $01xxxx for PC-I/O and extra I/O for org. system */
pin 14 = ORG;		/* $000000 - $00FFFF for the original system */

/* Boolean Equations */
ISA   = !(A23 # A22 # A21 # A20 # A19 # A18 # A17 # A16);
IOWR  = !PHI0 #  RW # A23 # A22 # A21 # A20 # A19 # A18 # !A17 # A16;
IORD  = !PHI0 # !RW # A23 # A22 # A21 # A20 # A19 # A18 # !A17 # A16;
SMEMW = !PHI0 #  RW # A23 # A22 # A21 # A20 # !(A19 # A18 # A17);
SMEMR = !PHI0 # !RW # A23 # A22 # A21 # A20 # !(A19 # A18 # A17);
MEMW  = !PHI0 #  RW # !(A23 # A22 # A21 # A20 # A19 # A18 # A17);
MEMR  = !PHI0 # !RW # !(A23 # A22 # A21 # A20 # A19 # A18 # A17);
EIO   = A23 # A22 # A21 # A20 # A19 # A18 # A17 # !A16;
/* IO    = A23 # A22 # A21 # A20 # A19 # A18 # A17 # !A16; */
ORG   = A23 # A22 # A21 # A20 # A19 # A18 # A17 #  A16;